Altera Cyclone III Reference Manual page 9

Altera Corporation
March 2008
64 MB flash memory
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FPGA configuration circuitry
MAX II CPLD and flash passive serial configuration
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On-board USB-Blaster
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Programmer
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On-board clocking circuitry
Two clock oscillators to support Cyclone III device user logic
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• 50-MHz
• 125-MHz
80 I/O, 6 clocks, SMBus, and JTAG
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SMA connector for external clock input and output
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General user and configuration interfaces
LEDs/displays:
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• Eight user LEDs
• One transmit/receive LED (TX/RX) per HSMC interface
• One configuration done LED
• Ethernet LEDs
• User 7-segment display
• Power consumption display
Memory activity LEDs:
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• SRAM
• FLASH
• DDR2 Top
• DDR2 Bottom
Push-buttons:
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• One user reset push-button (CPU reset)
• Four general user push-buttons
• One system reset push-button (user configuration)
• One factory push-button switch (factory configuration)
DIP switches:
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• One MAX control DIP switch
• One JTAG control switch
• Eight user DIP switches
Speaker header
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Displays
128 x 64 graphics LCD
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16 x 2 line character LCD
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Power supply
14 V - 20 V DC input
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On-board power measurement circuitry
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Up to 19.8 W per HSMC interface
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Mechanical
6"x 8" board
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Bench-top design
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Reference Manual
™
circuitry using the Quartus II
Cyclone III Development Board
Overview
1–3