Altera Cyclone III Reference Manual page 14

Board Overview
Table 2–1. Cyclone III Development Board (Part 3 of 3)
Board Reference
J10 SMA clock input
J11 SMA clock output
General User Input & Output
S1 through S4 User push buttons
S5 CPU reset push button
S6 and S7 Reset and factory
configuration push
buttons
D26 through D33 User LEDs
SW5 PGM CONFIG SELECT
SW4 Power select rotary
switch
U30 User display
J4 Character LCD
J13 Graphics LCD
Memory
U31 Flash
U23 and U24 SRAM
U11, U12, U13, DDR2 SDRAM
U25, U26
Components & Interfaces
U6 USB device
U3 Ethernet cable jack
J8, J9 HSMC Port A and Port B High speed mezzanine header allows for the connection of
Power Supply
J2 DC power jack
SW2 Input
2–4
Cyclone III Development Board
Type
SMA connector that allows the provision of an external clock
input.
SMA connector that allows the provision of an external clock
output.
Four 1.8 V push-button switches for user-defined, logic inputs.
One 1.8 V push-button switch for FPGA logic and CPU reset.
Two 1.8 V push-button switches that control FPGA
configuration from flash memory.
Eight user-defined LEDs.
Rotary switch to select which FPGA configuration file to use in
flash memory.
Power rail select for on-board power monitor.
User-defined, green 7-segment display
14-pin LCD display
30-position dot matrix graphics LCD display
64 MB of flash memory with a 16-bit data bus
The SRAM devices connect to the MAX II device as well as the
flash memory device.
Four x16 devices and a single x8 device.
USB device that provides JTAG programming of on-board
devices, including the Cyclone III device and flash memory
device.
The RF-45 jack is for Ethernet cable connection. The connector
is fed by a 10/100/1000 base T PHY device with an RGMII
interface to the Cyclone III device.
HSMC daughter cards.
14-20 V DC power source.
Switches the board's power on and off.
Reference Manual
Description
Altera Corporation
March 2008