Tektronix MSO70000C/DX Technical Reference page 76

Specifications (MSO70000C/DX, DPO70000C/DX, and DPO7000C series)
Setup-hold time violation trigger,
minimum clock pulse widths,
typical
≥4 GHz models
<4 GHz models
Pattern and state trigger, minimum
timing requirements, typical,
≥4 GHz models
Period trigger sensitivity, typical
≥4 GHz models
<4 GHz models
B trigger after events minimum
timing requirements, typical
≥4 GHz models
<4 GHz models
B trigger after events, event
counter range
≥4 GHz models
<4 GHz models
B trigger after time, time delay
range
≥4 GHz models
<4 GHz models
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Minimum time from active clock edge to
inactive edge
Hold times ≥ 0: Hold time + 550 ps
Hold times <0: Hold time + 1.6 ns
Minimum time from active clock edge to
inactive edge
Hold times ≥ 0: Hold time + 500 ps
Hold times <0: Hold time + 1.5 ns
The transition trigger event occurs at the end of the transition. The logic condition must be valid at
the moment the transition event occurs minus the setup time plus the hold time.
Pattern type
Time qualified pattern type
State type
1.5 divisions (at input connector)
1.0 division (at input connector)
Minimum pulse width
140 ps
Minimum pulse width
200 ps
1 to 2,000,000,000
1 to 10,000,000
3.2 ns to 3 Ms
5 ns to 250 s
MSO70000C/DX, DPO70000C/DX, DPO7000C, MSO5000/B, DPO5000/B Series
Minimum time from inactive clock edge to
active edge
500 ps
500 ps
Minimum time from inactive clock edge to
active edge
500 ps
Minimum Minimum
pulse width rearm time
150 ps 200 ps
150 ps 300 ps
1.7 GHz N.A.
Maximum counting frequency Minimum time between
3.5 GHz
Maximum counting frequency Minimum time between
Trigger specifications (cont.)
Setup time Hold time
N.A. N.A.
N.A. N.A.
25 ps 100 ps
channels
1 ns
channels
1 ns