Timing Chart - Hioki 3154 Instruction Manual

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6.1.7 Timing Chart

To control test voltage from external I/O, set signal before
testing. Test voltage cannot be changed during testing.
TEST signal timing is synchronized with front panel TEST lamp.
Delay time
Start testing
First judgment result
TEST signal OFF timing
START
(Input)
STOP
(Input)
TEST
(Output)
Test voltage
Measurement
Measurement
value display
PASS
(Output)
FAIL
(Output)
t
1
START signal range, STOP signal range
t
2
Between START input and TEST signal output
t
3 Between TEST signal output and measurement starting time
t
4
Sampling time
t
5
Between STOP signal input and time when test voltage starts falling.
t
6
Between time when test voltage stops and time when TEST
signal is disengaged.(HIGH)
Note: Reference value when measuring pure resistance 10 MΩ
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OFF
START signal
PASS
t
1
t
2
Stop
t
3
First
Continue to display
value from previous
test
Clear
Continue to display value from previous test
Timing
Resistance range
End testing
After second judgment result
SLOW
Occurrence
t t
4 4
Second
First Second
First measurement resulting in PASS judgment
Second and following measurement
resulting in FAIL judgment
59
Manual range
STOP signal
FAIL
t
1
t
5
t
6
Stop
Continue to
display
value from
final test
Continue to display
FAIL judgment
Time
60 ms min.
80 ms max.
Approx. 250 ms
FAST 0.1 s/SLOW 1 s
80 ms max.
Test voltage: 25 V
approx. 150 ms
Test voltage: 1000 V
approx. 600 ms
External Interface