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Chapter 3:
Boundary-Scan and JTAG Configuration
68
Power-Up
No
V
> 1.0 V
CCINT
Yes
Keep Clearing
Yes
PROGRAM_B
Configuration
Memory
Clear Configuration
Memory Once More
No
INIT_B = High?
Yes
Sample
JTAG Available
Mode Pins
Load CFG_IN
Instruction
Load
Bitstream
No
CRC
Abort Startup
Correct?
Yes
Synchronous
(Clock five 1s
on TMS)
TAP Reset
Load JSTART
Instruction
Startup
Sequence
Reconfigure?
Operational
Figure 3-6: Device Configuration Flow Diagram
www.xilinx.com
Low?
Load
Shutdown
JSHUTDOWN
Sequence
Instruction
Yes
No
ug071_40_073007
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
R
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