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R
finished. (This can require several CCLK pulses after DONE goes High. See
8)" in Chapter 1
After configuration, the CS_B and RDWR_B signals can be deasserted, or they can remain
asserted. Because the SelectMAP port is inactive, toggling RDWR_B at this time does not
cause an abort.
continuous data loading.
PROGRAM_B
INIT_B
CCLK
(1)
CS_B
(2)
RDWR_B
DATA[0:7]
BUSY
DONE
Notes relevant to
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. After the last byte is loaded, the device enters the startup sequence.
11. The startup sequence lasts a minimum of eight CCLK cycles. See
12. The DONE pin goes High during the startup sequence. Additional CCLKs can be
13. After configuration has finished, the CS_B signal can be deasserted.
14. After the CS_B signal is deasserted, RDWR_B can be deasserted.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
for details).
Figure 2-16
(4)
(6)
(5)
(8)
Byte 0
(3)
(7)
High-Z
Figure 2-16: Continuous SelectMAP Data Loading
Figure
2-16:
CS_B signal can be tied Low if there is only one device on the SelectMAP bus. If CS_B
is not tied Low, it can be asserted at any time.
RDWR_B can be tied Low if readback is not needed. RDWR_B should not be toggled
after CS_B has been asserted, because this triggers an ABORT. (See
ABORT").
If CS_B is tied Low, BUSY is tristated and pulled up until INIT_B toggles High.
The MODE pins are sampled when INIT_B goes High.
RDWR_B should be asserted before CS_B to avoid causing an abort.
CS_B is asserted, enabling the SelectMAP interface.
BUSY remains in high-Z state until CS_B is asserted.
With 8-bit SelectMAP, the first byte is loaded on the first rising CCLK edge after CS_B
is asserted.
The configuration bitstream is loaded one byte per rising CCLK edge.
Chapter 1
required to complete the startup sequence. (See
www.xilinx.com
summarizes the timing of SelectMAP configuration with
(9)
(10)
(11)
Byte 1
Byte n
"Startup (Step 8)" in Chapter
SelectMAP Configuration Interface
"Startup (Step
(13)
(14)
(12)
ug071_25_073007
"SelectMAP
"Startup (Step 8)" in
1).
47
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