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R
Single Device Configuration
Table 3-6
Refer to
automatically if configuring the part with the iMPACT software.
Table 3-6:
Single Device Configuration Sequence
TAP Controller Step and Description
1.
On power-up, place a logic 1 on the TMS, and clock
the TCK five times. This ensures starting in the TLR
(Test-Logic-Reset) state.
2.
Move into the RTI state.
3.
Move into the SELECT-IR state.
4.
Enter the SHIFT-IR state.
5.
Start loading the CFG_IN instruction, LSB first:
6.
Load the MSB of CFG_IN instruction when exiting
SHIFT-IR, as defined in the IEEE standard.
7.
Enter the SELECT-DR state.
8.
Enter the SHIFT-DR state.
9.
Shift in the Virtex-4 bitstream. Bit
(1)
bit in the bitstream
.
10.
Shift in the last bit of the bitstream. Bit
on the transition to EXIT1-DR.
11.
Enter UPDATE-DR state.
12.
Reset TAP by clocking five 1s on TMS
13.
Enter the SELECT-IR state.
14.
Move to the SHIFT-IR state.
15.
Start loading the JSTART instruction. The JSTART
instruction initializes the startup sequence.
16.
Load the last bit of the JSTART instruction.
17.
Move to the UPDATE-IR state.
18.
Move to the RTI state and clock the startup
sequence by applying a minimum of 12 clock cycles
to the TCK.
19.
Move to the TLR state. The device is now
functional.
Notes:
1. In the Configuration Register, data is shifted in from the right (TDI) to the left (TDO), MSB first. (Shifts into the Configuration Register are
different from shifts into the other registers in that they are MSB first.)
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
describes the TAP controller commands required to configure a Virtex-4 device.
Figure 3-2
for TAP controller states. These TAP controller commands are issued
(MSB) is the first
n
(LSB) shifts
0
www.xilinx.com
Set & Hold
TDI
X
X
X
X
111000101
1
X
X
bit
... bit
1
n
bit
0
X
X
X
X
111001100
1
X
X
X
# of Clocks
TMS
TCK
1
5
0
1
1
2
0
2
0
9
1
1
1
2
0
2
(bits in
0
bitstream)-1
1
1
1
1
1
5
1
2
0
2
0
9
1
1
1
1
0
12
1
3
69
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