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Chapter 8:
Readback and Configuration Verification
Table 8-5: Shutdown Readback Command Sequence (JTAG) (Continued)
108
Step
Description
Remain in RTI for 12 TCK cycles.
5
Move into the Select-IR state.
Move into the Shift-IR State.
Shift the first 9 bits of the CFG_IN instruction,
LSB first.
Shift the MSB of the CFG_IN instruction while
6
exiting SHIFT-IR.
Move into the SELECT-DR state.
Move into the SHIFT-DR state.
Shift configuration packets into the CFG_IN
data register, MSB first.
7
Shift the LSB of the last configuration packet
while exiting SHIFT-DR.
Move into the SELECT-IR State.
Move into the SHIFT-IR State.
Shift the first 9 bits of the CFG_OUT
instruction, LSB first.
Shift the MSB of the CFG_OUT instruction
8
while exiting Shift-IR.
Move into the SELECT-DR state.
Move into the SHIFT-DR state.
Shift the contents of the FDRO register out of
the CFG_OUT data register.
Shift the last bit of the FDRO register out of the
9
CFG_OUT data register while exiting SHIFT-
DR.
Move into the Select-IR state.
Move into the Shift-IR State.
End by placing the TAP controller in the TLR
10
state.
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Set and Hold
TDI
TMS
X
0
X
1
X
0
0
111000101
1
1
X
1
X
0
a: 0xFFFFFFFF
b: 0xAA995566
c: 0x20000000
d: 0x30008001
e: 0x00000004
f: 0x30002001
0
g: 0x00000000
h: 0x28006000
i: 0x48024090
j: 0x20000000
0x20000000
0
1
X
1
X
0
111000100
0
(CFG_OUT)
1
1
X
1
X
0
...
0
X
1
X
1
X
0
X
1
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
R
# of Clocks
(TCK)
12
2
2
9
1
2
2
351
1
3
2
9
1
2
2
number of
readback
bits – 1
1
3
2
5
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