Xilinx Virtex-4 Configuration User Manual page 14

Chapter 1: Configuration Overview
The terms Master and Slave refer to the direction of the configuration clock (CCLK):
•
•
The JTAG/Boundary-Scan configuration interface is always available, regardless of the
MODE pin settings. The JTAG/Boundary-Scan configuration mode disables all other
configuration modes. This prevents conflicts between configuration interfaces.
The JTAG interface is available after the mode pins are sampled. Activating PROGRAM_B
disables JTAG until INIT is completed.
Certain pins are dedicated to configuration, while others are dual-purpose
Dual-purpose pins serve both as configuration pins and as user I/O after configuration.
Dedicated configuration pins retain their function after configuration.
Table 1-2: Virtex-4 Configuration Pins
(1)
Pin Name Type
M[2:0] Input
CCLK Input or
Output
D_IN Input
DOUT_BUSY Output
DONE Bidirectional,
Open-Drain
or Active
INIT_B Input or
Output,
Open-Drain
PROGRAM_B Input
SelectMAP Bidirectional
Data
14
In Master configuration modes, the Virtex-4 device drives the configuration clock
(CCLK) from an internal oscillator
In Slave configuration modes, the configuration clock is an input.
Dedicated or
(2)
Dual-Purpose
Dedicated Mode pins that determine configuration mode. Sampled on the rising
edge of INIT_B.
Dedicated Configuration clock source for all configuration modes except JTAG.
Dedicated Serial data input for serial configuration modes.
Dedicated In Serial configuration mode, pin acts as serial data output for daisy-chain
configuration. In SelectMAP mode, pin acts as BUSY output.
Dedicated Active High signal indicating configuration is complete.
0 = FPGA not configured
1 = FPGA configured
Refer to the "BitGen" section of the Development System Reference Guide for
software settings.
Dedicated Before MODE pins are sampled, INIT_B is an input that can be held Low
to delay configuration.
After MODE pins are sampled, INIT_B is an open-drain active Low
output indicating whether a CRC error occurred during configuration:
0 = CRC error
1 = No CRC error
Dedicated Active Low asynchronous full-chip reset.
Dual-Purpose Parallel data inputs for SelectMAP modes.
For 8-bit SelectMAP:
D0 = MSB
D7 = LSB
For 32-bit SelectMAP:
D0 = LSB
D31 = MSB
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(Table
Description
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
R
1-2).