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R
4.
5.
6.
Table 8-4: Status Register Readback Command Sequence (JTAG)
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
c.
Write the read STAT register packet header to the device.
d. Write two dummy words to the device to flush the packet buffer.
The MSB of all configuration packets sent through the CFG_IN register must be sent
first. The LSB is shifted while moving the TAP controller out of the SHIFT-DR state.
Shift the CFG_OUT instruction into the JTAG Instruction Register through the Shift-IR
state. The LSB of the CFG_OUT instruction is shifted first; the MSB is shifted while
moving the TAP controller out of the SHIFT-IR state.
Shift 32 bits out of the Status register through the Shift-DR state.
Reset the TAP controller.
Step
Description
Clock five 1s on TMS to bring the device to the
TLR state.
Move into the RTI state.
1
Move into the Select-IR state.
Move into the Shift-IR state.
Shift the first 9 bits of the CFG_IN instruction,
LSB first.
Shift the MSB of the CFG_IN instruction while
2
exiting SHIFT-IR.
Move into the SELECT-DR state.
Move into the SHIFT-DR state.
Shift configuration packets into the CFG_IN
data register, MSB first.
3
Shift the LSB of the last configuration packet
while exiting SHIFT-DR.
Move into the SELECT-IR state.
Move into the SHIFT-IR state.
Shift the first 9 bits of the CFG_OUT instruction,
LSB first.
Shift the MSB of the CFG_OUT instruction
4
while exiting Shift-IR.
Move into the SELECT-DR state.
Move into the SHIFT-DR state.
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Readback Command Sequences
Set and Hold
TDI
TMS
X
1
X
0
X
1
X
0
111100101
0
(CFG_IN)
1
1
X
1
X
0
a: 0xAA995566
b: 0x20000000
c: 0x2800E001
0
d: 0x20000000
0x20000000
0
1
X
1
X
0
1110001101
0
(CFG_OUT)
1
1
X
1
X
0
# of
Clocks
(TCK)
5
1
2
2
9
1
2
2
159
1
3
2
9
1
2
2
105
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