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R
Figure 2-7
receivers. The stub at CCLK input 1 has a length constraint.
Figure 2-8
CCLK receivers (four in this example). All CCLK inputs except input 4 have length
constraints.
CCLK
Output
(50 Ω)
Z
0
Figure 2-8: Multi-Drop: One CCLK Output, More Than Two CCLK Inputs
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
shows the basic multi-drop flyby topology for one CCLK driver and two CCLK
CCLK
Output
(50 Ω)
Z
0
length < 8mm
Figure 2-7: Multi-Drop: One CCLK Output, Two CCLK Inputs
shows the multi-drop flyby topology for one CCLK driver and more than two
(50 Ω)
Z
Z
0
CCLK
CCLK
Input 1
Input 2
www.xilinx.com
Serial Configuration Interface
(50 Ω)
Z
0
CCLK
Input 1
(50 Ω)
(50 Ω)
Z
0
0
CCLK
Input 3
CCLK
Input 2
V
CCO_0
(100 Ω)
2 x Z
0
(100 Ω)
2 x Z
0
ug071_2_07_072505
CCLK
Input 4
V
CCO_0
(100 Ω)
2 x Z
0
(100 Ω)
2 x Z
0
ug071_2_08_072505
35
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