Xilinx Virtex-4 Configuration User Manual page 43

R
Otherwise, RDWR_B can be tied Low and BUSY can be ignored. Unlike earlier Virtex
devices, the BUSY signal never needs to be monitored when configuring Virtex-4 devices.
Refer to
Notes relevant to
1.
2.
3.
4.
5.
6.
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
"Bitstream Loading (Steps 4-7)" in Chapter 1
DATA[0:7]
CCLK
WRITE
BUSY
CS(0)
(1) (2)
DONE
INIT
PROGRAM
Figure 2-14: Multiple Slave Device Configuration on an 8-bit SelectMAP Bus
Figure 2-14:
The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver must be disabled.
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
The BUSY signals can be left unconnected if readback is not needed.
An external controller such as a microprocessor or CPLD is needed to control
configuration.
The CCLK net requires Thevenin parallel termination. See
Configuration Clock (CCLK)," page
www.xilinx.com
SelectMAP Configuration Interface
and to
M1 M2
M0
Virtex-4
Slave
SelectMAP
D[0:7]
CCLK
RDWR_B
BUSY
CS(1)
CS_B
PROGRAM_B
INIT_B
DONE
34.
Chapter 8.
(6)
(6)
M1 M2
M0
Virtex-4
Slave
SelectMAP
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
PROGRAM_B
INIT_B
DONE
ug071_20_073007
"Board Layout for
43