Xilinx Virtex-4 Configuration User Manual page 31

R
Notes relevant to
1.
2.
3.
4.
5.
6.
7.
The first device in a serial daisy chain is the first to be configured. No data is passed onto
the DOUT pin until all the data frames, the start-up command, and CRC check have been
loaded. CRC checks only include the data for the current device, not for any others in the
chain. (See
After the first device in the chain finishes configuration and passes its CRC check, it enters
the Start-Up sequence. At the Release DONE pin phase in the Start-Up sequence, the device
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Xilinx
(7)
Serial PROM
DATA
CLK
CE
RESET/OE
(7)
PROGRAM
Figure 2-4: Master/Slave Serial Mode Daisy Chain Configuration
Figure 2-4:
The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. For all devices except the last, the
active driver on DONE must be disabled. For the last device in the chain, the active
driver on DONE can be enabled. See
Daisy Chains."
The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
The BitGen startup clock setting must be set for CCLK for serial configuration. The
oscillator frequency can be selected in BitGen (default is 4 MHz). Selectable
frequencies are 4, 5, 7, 8, 9, 10, 13, 15, 20, 26, 30, 34, 41, 45, 51, 55, and 60 MHz. Because
the oscillator can vary by ± 50%, select a maximum frequency not to exceed the F
of the configuration device.
The PROM in this diagram represents one or more Xilinx serial PROMs. Multiple serial
PROMs can be cascaded to increase the overall configuration storage capacity.
The .bit file must be reformatted into a PROM file before it can be stored on the serial
PROM. Separate bitstream files cannot be concatenated together to form a daisy-chain
bitstream. Refer to the "Generating PROM Files"
On XC17V00 PROMs, the reset polarity is programmable. RESET should be set for
active Low when using an XC17V00 device in this setup.
The CCLK net requires Thevenin parallel termination. See
Configuration Clock (CCLK)," page
"Cyclic Redundancy Check (Step 7)" in Chapter
www.xilinx.com
Serial Configuration Interface
M0 M1
M2
DIN DOUT
CCLK
Virtex-4
Master
Serial
(2)
PROGRAM_B
DONE INIT_B
"Guidelines and Design Considerations for Serial
section.
34.
M0 M1
M2
DIN DOUT
CCLK
Virtex-4
Slave
Serial
(1)
PROGRAM_B
DONE INIT_B
ug071_17_073007
MAX
"Board Layout for
1.)
31