Xilinx Virtex-4 Configuration User Manual page 3

Version
01/19/06 1.4
01/12/07 1.5
06/21/07 1.6
07/30/07 1.7
08/08/07 1.8
10/01/07 1.9
04/08/08 1.10
06/09/09 1.11
UG071 (v1.12) June 2, 2017
Completed grammatical and style edits for clarity and compliance to Xilinx
documentation standards.
Added preface, not included in previous versions. Corrected
Added "HSWPEN has a weak pull-up prior to and during configuration" to
page 14. Clarified first paragraph of
Initialization)," page 16. Clarified title of
differentiate from Figure 1-10
EOS, DCI_MATCH, and DCM_LOCK to
supported with an encrypted bitstream in the LX, SX, and FX12 devices" as last
paragraph in "Loading the Encryption Key," page 24
in "Bitstream Encryption and Internal Configuration Access Port (ICAP)," page
Added third paragraph to
SelectMAP Data Pin Description in
Reconfiguration," page 51. Added first paragraph to
page 75. Updated the BitGen option to DONE_CYCLE:KEEP in
Register," page 77. Added
Configuration Data in Table 8-2, page 103
DESYNC (throughout).
Updated notes relevant to
Register" section. Added the
Updated the "Control Register (CTL)"
Updated "Introduction,"Table
Loading," Chapter 5, "User Access Register," "Changing the Multiply and Divide
Values," "Dynamic Phase Shifting Through the DRP in Direct Mode," Table
address value in Table 7-5,
Table 8-2. Added "Packet
Added TAP controller state definitions in the
to Table 8-1.
Replaced instructions for setting a direct phase shift value in the
Shifting Through the DRP in Direct Mode"
Title: Updated corporate disclaimer.
Chapter 2: Updated notes relevant to
Chapter 3: Updated "TAP Controller"
Chapter 8: Updated Table
Chapter 1: Updated Table 1-6
Chapter 3: Updated "Identification Register"
Chapter 1:
• Interchanged phase events 5 and 6 in
Chapter 2:
• Added cross reference to the
• Changed default oscillator frequency to 4 MHz in Note 3 following
• Updated
"Single Device SelectMAP Configuration"
Chapter 8:
• Updated description of .rba and .rbb files in
www.xilinx.com
Revision
"Clear Configuration Memory (Step 2,
Table 1-10, page 22
(signal sequencing). Added descriptions for GWE, GTS,
Table 1-10, page
"Loading Encrypted Bitstreams," page
Table 2-4, page 39. Added port width to
"Frame Address Register (FAR)," page
(step 4 and step 6). Changed DESYCH to
Figure 2-5. Updated Table
"ICAP - Internal Configuration Access Port"
section, Table
1-2, "Master Serial Configuration," "SelectMAP Data
"Configuration Memory Read Procedure (SelectMAP),"
Types"section.
"TAP Controller"
section.
Figure 2-3 and updated
section.
8-5.
and "Loading Encrypted Bitstreams"
section, including
Table 1-9.
Virtex-4 FPGA Data
"Verifying Readback Data"
Virtex-4 FPGA Configuration User Guide
Table 1-1, page 13
(status register), to
22. Added "ICAP is not
and as last line in first paragraph
24. Clarified
"SelectMAP
Chapter 4, "Frame ECC Logic,"
Chapter 5, "User Access
92. Corrected
2-4, Table 3-3, and the "Instruction
section.
7-7, and Figure 8-2.
section and a NOOP note
"Dynamic Phase
Figure 2-19.
section.
Table 3-4 and
Sheet.
Figure
section.
(Note 2.).
Table 1-2,
25.
7-1, CBC
and
Table 3-5.
2-4.
section.