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R
Table 7-10: Configuration Options Register Description (Continued)
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Name
SINGLE
OSCFSEL
SSCLKSRC
DONE_CYCLE
MATCH_CYCLE
LOCK_CYCLE
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Bit Index
Readback is not single-shot
0:
New captured values are loaded on each successive
CAP assertion on the CAPTURE_VIRTEX4
primitive. Capture can also be performed with the
23
GCAPTURE instruction in the CMD register.
Readback is single-shot.
1:
The RCAP instruction must be loaded into the CMD
register between successive readbacks.
Select CCLK frequency in Master configuration
22:17
modes.
Startup-sequence clock source.
00: CCLK
16:15
01: UserClk (per connection on the
CAPTURE_VIRTEX4 block)
1x: JTAGClk
Startup cycle to release the DONE pin.
001: Startup cycle 2
010: Startup cycle 3
14:12
011: Startup cycle 4
100: Startup cycle 5
101: Startup cycle 6
Startup cycle to stall in until DCI matches.
000: Startup cycle 1
001: Startup cycle 2
010: Startup cycle 3
11:9
011: Startup cycle 4
100: Startup cycle 5
101: Startup cycle 6
111: No Wait
Startup cycle to stall in until DCMs lock.
000: Startup cycle 1
001: Startup cycle 2
010: Startup cycle 3
8:6
011: Startup cycle 4
100: Startup cycle 5
101: Startup cycle 6
111: No Wait
Configuration Control Logic
Description
95
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