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Chapter 2:
Configuration Interfaces
Figure 2-9
CCLK inputs. The branch point creates a significant impedance discontinuity. This
arrangement is Not Recommended.
Daisy-Chaining Virtex-4 with Earlier FPGA Generations
A serial daisy chain can include earlier generations of Xilinx FPGAs (Virtex-II, Virtex,
Spartan-II, 4000, etc.). In general, newer devices should appear upstream of older devices.
For example, a daisy chain consisting of a Virtex-4, a Virtex-II, a Virtex, and a 4000E device
should be arranged with the Virtex-4 device first in the chain, the Virtex-II device second,
the Virtex device third, and the 4000E device last.
BitGen Options for Mixed Daisy Chains
All Virtex-based device families have similar BitGen options. The guidelines provided for
Virtex-4 BitGen options should be applied to all Virtex-based devices in a serial daisy
chain.
If 4000-series devices are included in the daisy chain, it is important to set the BitGen
SyncToDONE option for the startup settings.
36
shows a star topology where the transmission line branches to the multiple
Impedance
Discontinuity
CCLK
Output
Z
0
Figure 2-9: Not Recommended
Star Topology: One CCLK Output, Two CCLK Inputs
www.xilinx.com
CCLK
Input 1
Z
0
CCLK
Input 2
Z
0
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
R
ug071_2_09_080204
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