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Table 3-3: Virtex-4 Boundary-Scan Instructions
Boundary-Scan Command
EXTEST
SAMPLE
USER1
USER2
USER3
USER4
CFG_OUT
CFG_IN
INTEST
USERCODE
IDCODE
HIGHZ
JPROGRAM
JSTART
JSHUTDOWN
ISC_ENABLE
ISC_PROGRAM
ISC_PROGRAM_SECURITY
ISC_ADDRESS_SHIFT
ISC_NOOP
ISC_READ
ISC_DISABLE
BYPASS
RESERVED
Notes:
1. For FX devices with two processors, the instruction codes are MSB extended with 1s. For example, the CFG_IN instruction is
1111 1111 000101.
IR[9:6]
TDI →
Reserved
Figure 3-4: Virtex-4 Instruction Capture Values Loaded into IR as Part of an Instruction Scan Sequence
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
Boundary-Scan for Virtex-4 Devices Using IEEE Standard 1149.1
Binary Code
(9:0)
Enables Boundary-Scan EXTEST operation
1111000000
Enables Boundary-Scan SAMPLE operation
1111000001
Access user-defined register 1
1111000010
Access user-defined register 2
1111000011
Access user-defined register 3
1111100010
Access user-defined register 4
1111100011
Access the configuration bus for readback
1111000100
Access the configuration bus for configuration
1111000101
Enables Boundary-Scan INTEST operation
1111000111
Enables shifting out user code
1111001000
Enables shifting out of ID code
1111001001
3-state output pins while enabling Bypass Register
1111001010
Equivalent to and has the same affect as PROGRAM
1111001011
Clocks the start-up sequence when StartClk is TCK
1111001100
Clocks the shutdown sequence
1111001101
Marks the beginning of ISC configuration. Full shutdown is executed
1111010000
Enables in-system programming
1111010001
Change security status from secure to non-secure mode and vice versa
1111010010
For programming, key address is shifted first, before the key
1111010011
No operation
1111010100
Used to read back BBR
1111010101
Completes ISC configuration. Startup sequence is executed
1111010111
Enables BYPASS
1111111111
All other codes
Xilinx reserved instructions
IR[5]
IR[4]
DONE
INIT
www.xilinx.com
Description
IR[3]
IR[2]
ISC_ENABLED
ISC_DONE
IR[1:0]
→ TDO
0 1
63
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