Table of Contents
Advertisement
Chapter 2:
Configuration Interfaces
Table 2-2
Table 2-2: Virtex-4 Serial Configuration Interface Pins
28
Figure 2-1: Virtex-4 Serial Configuration Interface
describes the Serial Configuration Interface.
Pin Name
Type
M[2:0]
Input
Input or
CCLK
Output
D_IN
Input
DOUT_BUSY
Output
Bidirectional,
DONE
open-drain
or active
Input or
INIT_B
Output,
open-drain
PROGRAM_B
Input
www.xilinx.com
M[2:0]
DOUT
D_IN
INIT_B
PROGRAM_B
DONE
CCLK
ug071_14_073007
Dedicated
or Dual-
Purpose
Dedicated
Mode Pins – determine configuration mode.
Configuration clock source for all configuration
Dedicated
modes except JTAG.
Serial configuration data input, synchronous to
Dedicated
rising CCLK edge.
Serial data output for downstream daisy-chained
Dedicated
devices.
Active High signal indicating configuration is
complete:
0 = FPGA not configured
Dedicated
1 = FPGA configured
Refer to the "BitGen" section of the Development
System Reference Guide for software settings.
Before the MODE pins are sampled, INIT_B is an
input that can be held Low to delay configuration.
After the MODE pins are sampled, INIT_B is an
Dedicated
open-drain active Low output indicating whether
a CRC error occurred during configuration:
0 = CRC error
1 = No CRC error
Dedicated
Active-Low asynchronous full-chip reset.
Virtex-4 FPGA Configuration User Guide
Description
UG071 (v1.12) June 2, 2017
R
Advertisement
Table of Contents
