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Synchronous timing for the port is provided by the DCLK input, and all the other input
signals are registered in the functional block on the rising edge of DCLK. Input (write) data
is presented simultaneously with the write address and DWE and DEN signals prior to the
next positive edge of DCLK. The port asserts DRDY for one clock cycle when it is ready to
accept more data. The timing requirements relative to DCLK for all the other signals are the
same. The output data is not registered in the functional blocks. Output (read) data is
available after some cycles following the cycle that DEN and DADDR are asserted. The
availability of output data is indicated by the assertion of DRDY.
Figure 6-4
and read operations. Absolute timing parameters, such as maximum DCLK frequency,
setup time, etc., are defined in the
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
and
Figure 6-5
show the timing relationships between the port signals for write
DCLK
DEN
DRDY
DWE
DADDR[m:0]
DI[n:0]
DO[n:0]
Figure 6-4: Write Timing with Wait States
DCLK
DEN
DRDY
DWE
DADDR[m:0]
DI[n:0]
DO[n:0]
Figure 6-5: Read Timing with Wait States
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Dynamic Reconfiguration of Functional Blocks (DRP)
Virtex-4 FPGA Data
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