Xilinx Virtex-4 Configuration User Manual page 40

Chapter 2: Configuration Interfaces
Table 2-4: Virtex-4 SelectMAP Configuration Interface Pins (Continued)
Notes:
1. If SelectMAP32 is used and the bitstream is compressed by the -g compress in BitGen then the
2. If the SelectMAP interface is not used, the CS_B and RDWR_B pins can be left unconnected. Weak
40
Pin Name Type
Three-State
DOUT_BUSY
Output
Bidirectional,
DONE Open-Drain
or active
Input or
INIT_B Output,
Open-Drain
PROGRAM_B Input
CS_B Input
RDWR_B Input
CONFIG_MODE constraint must be used. the values for the CONFIG_MODE constraint are either
S_SelectMAP32 or S_SelectMAP32+READBACK. S_SelectMAP32+READBACK preserves the
S_SelectMAP32 data pins for readback (also known as persist).
pullups pull these pins High, and their state is ignored.
www.xilinx.com
Dedicated
or Dual-
Purpose
Indicates that the device is not ready to send
readback data. For Virtex-4 devices, the BUSY
Dedicated signal is only needed for readback; it is not needed
for configuration (see
Loading").
Active High signal indicating configuration is
complete:
Dedicated
0 = FPGA not configured
1 = FPGA configured
Before MODE pins are sampled, INIT_B is an
input that can be held Low to delay configuration.
After MODE pins are sampled, INIT_B is an open-
drain active Low output indicating whether a CRC
Dedicated
error occurred during configuration:
0 = CRC error
1 = No CRC error
Dedicated Active-Low asynchronous full-chip reset
Active-Low chip select to enable the SelectMAP
data bus (see "SelectMAP Data
Dedicated
0 = SelectMAP data bus enabled
= SelectMAP data bus disabled
1
Determines the direction of the SelectMAP data
bus (see "SelectMAP Data
0 = inputs
Dedicated = outputs
1
RDWR_B input can only be changed while CS_B is
deasserted, otherwise an ABORT occurs (see
"SelectMAP ABORT")
Virtex-4 FPGA Configuration User Guide
Description
"SelectMAP Data
Loading"):
(2)
Loading"):
(2)
.
UG071 (v1.12) June 2, 2017
R