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R
8.
9.
10. Reset the TAP controller.
Table 8-5: Shutdown Readback Command Sequence (JTAG)
Virtex-4 FPGA Configuration User Guide
UG071 (v1.12) June 2, 2017
h. Write the read FDRO register Type-1 packet header to the device.
i.
Write a Type-2 packet header to indicate the number of words to read from the
device.
j.
Write two dummy words to the device to flush the packet buffer.
The MSB of all configuration packets sent through the CFG_IN register must be sent
first. The LSB is shifted while moving the TAP controller out of the SHIFT-DR state.
Shift the CFG_OUT instruction into the JTAG Instruction Register through the
Shift-DR state. The LSB of the CFG_OUT instruction is shifted first; the MSB is shifted
while moving the TAP controller out of the SHIFT-IR state.
Shift frame data from the FDRO register through the Shift-DR state.
Step
Description
Clock five 1s on TMS to bring the device to the
TLR state.
Move into the RTI state.
1
Move into the Select-IR state.
Move into the Shift-IR State.
Shift the first 9 bits of the CFG_IN instruction,
LSB first.
Shift the MSB of the CFG_IN instruction while
2
exiting Shift-IR.
Move into the SELECT-DR state.
Move into the SHIFT-DR state.
Shift configuration packets into the CFG_IN
data register, MSB first.
3
Shift the LSB of the last configuration packet
while exiting SHIFT-DR.
Move into the SELECT-IR State.
Move into the SHIFT-IR State.
Shift the first 9 bits of the JSHUTDOWN
instruction, LSB first.
Shift the MSB of the JSHUTDOWN
4
instruction while exiting SHIFT-IR.
Move to RTI.
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Readback Command Sequences
Set and Hold
# of Clocks
TDI
TMS
X
1
X
0
X
1
X
0
0
111000101
1
1
X
1
X
0
a: 0xFFFFFFFF
b: 0xAA995566
c: 0x20000000
d: 0x30008001
0
0x00000007
e: 0x20000000
0x20000000
0
1
X
1
X
0
0
111000110
1
1
1
X
0
(TCK)
5
1
2
2
9
1
2
2
223
1
3
2
9
1
1
1
107
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