I/O Port Offset 0Fh: Fpga Register Data Port; Watchdog Register: Fpga Index - 03H; Watchdog Index Mode; Table 4-14. Fpga Register Data Port - Motorola CPV5000 Installation And Reference Manual

Functional Description

I/O port offset 0Fh: FPGA register data port

All communication of data from the CPV5000 is implemented through the
FPGA register data port. The function of each bit is dependent on the data in
the I/O port offset 0Dh: FPGA register index port.
4
Bit 7
Function

Watchdog register: FPGA index - 03h

The watchdog timer is designed to be used in critical control applications. The
function of the watchdog is to stop a program or part of the hardware from
going into a runaway or locked out mode.

Watchdog index mode

When the timer is enabled, the watchdog strobe register must be written to at
regular intervals to stop the watchdog from triggering. The exact data that is
written is irrelevant. It is the write operation to the register that resets the
watchdog timer.
The watchdog has four modes when triggered:
The watchdog is enabled by writing 03h to ISA I/O offset 00Dh (Index), then
writing data to the control register at ISA I/O offset 00Fh.
4-20

Table 4-14. FPGA register data port

6 5 4
Data from or to the selected FPGA register
1. Disabled
2. Set the WD bit in the watchdog strobe register (073h)
3. Item 2 + Assert IOCHK
4. Item 3 + Reset the CPV5000.
3 2 1 0