Siemens siprotec 7SA522 User Manual page 490

Installation and Commissioning
Blocking Scheme
Permissive Under-
reach Transfer
8-34
A short-circuit in Z1B, but outside Z1, is simulated. This may be done with secondary
injection test equipment. As the device at the opposite line end is not picked up, the
echo function comes into effect there, and a trip command at the line end initiating the
test, results.
If no trip command results, the transmission path must be checked again, in particular
that the echo signals are assigned to the transmit outputs.
This test must be executed at both line ends. For three terminal lines, it must be done
at each line end, for each transmission path.
The functioning of the echo delay time and the derivation of the circuit breaker switch-
ing status should also be tested at this time (the functioning of the protection at the
opposite line end is tested):
The circuit breaker of the feeder to which the protection belongs must be open, as is
the circuit breaker at the opposite end of this line. As before, a fault is again simulated.
A receive signal impulse delayed by a little more than twice the signal transmission
time, should appear via the echo from the opposite line end; the device should also
issue a trip command.
The circuit breaker at the opposite line end should now be closed (with open isolators).
After simulation of the same fault, a receive signal again appears and a trip command
is again issued. However this time the receive signal is additionally delayed by the
echo delay time of the device at the opposite line end (0,04 s presetting, address 
7ULS(FKR '(/$<).
If the echo delay response is opposite to the above description, the mode of operation
of the corresponding binary inputs (H–active/L–active) at the opposite line end must
be corrected (refer to Sub-section 5.2.4).
The circuit breaker must be opened again. This test must also be carried out at both
line ends, in the case of three terminal lines, at each end, for each transmission path.
Prerequisites are: 7HOHSURWHFWLRQ IRU 'LVWDQFH SURW 7HOHSURW
'LVW in address  (section 5.1) is set to the overreach transfer with a blocking
signal i.e. %ORFNLQJ; furthermore, the setting in address  must be set to )&7
7HOHS () 21. Naturally, the corresponding send and receive signals must also be
assigned to the corresponding binary output and input.
In the case of the blocking scheme, communication between the line ends is neces-
sary.
On the transmitting end, a fault in the reverse direction is simulated, while at the re-
ceiving end a fault in Z1B but beyond Z1 is simulated. This may be achieved with sec-
ondary injection test equipment at each end. As long as the transmitting end is trans-
mitting, the receiving end may not generate a trip signal, unless this results from a
higher distance stage. After removal of the simulated fault at the transmitting end, the
receiving end remains blocked for the additional duration of the transmit prolongation
time of the transmitting end (6HQG 3URORQJ, address ). The transient blocking
time of the receiving end (7U%ON %ORFN7LPH, address ) will additionally appear
if a finite waiting time 7U%ON :DLW 7LPH (address  ) was set and if this time had
been exceeded.
This test must be carried out at both line ends, on a three terminal line at each line end
for each transmission path.
Prerequisite: 7HOHSURWHFWLRQ IRU 'LVWDQFH SURW 7HOHSURW 'LVW in
address  (Section 5.1) is set to the permissive underreach transfer trip mode, i.e.
3877; furthermore the setting in address  must be set to )&7 7HOHS () 21.
7SA522 Manual
C53000-G1176-C119-2