Procedure - Analog Devices AD9361 Reference Manual

UG-570

PROCEDURE

1. Connect all AD9361 clock inputs to a common buffered
reference using the XTALN pin as shown in Figure 59 for
proper synchronization. (Figure 59 uses the
configured as a clock buffer amplifier.) In addition, the
electrical length of the trace feeding the reference to each
device must be equivalent to avoid clock skew that could
cause the sync function to fail.
2. After power-up, set each BBPLL to the same frequency by
sending the same frequency command to each device.
3. Determine standard register settings that will generate the
same internal sampling clocks and DATA_CLK outputs
using the customer software and write them to each device.
4. In each device set the MCS BBPLL Enable and MCS BB
Enable bits and then set the MCS refclk Scale En bit. This
enables multichip synchronization (MCS) for the BBPLLs
and references the proper internal clock.
5. Input a rising-edge pulse to the SYNC_IN pin of each
device. The timing requirements of this signal are
illustrated in Figure 60 for the case where the internal
BBPLL REF_CLK is a buffered version of the external
REF_CLK and in Figure 61 for the case where the internal
BBPLL REF_CLK is 2× the external REF_CLK. MCS
REF_CLK
SYNC_IN
Figure 60.
REF_CLK
SYNC_IN
Figure 61.
ADA4851-4
t
CLK
t 1/f
=
CLK REF_CLK
t
OUTPUT DELAY: = 1ns MINIMUM
OD
t
SETUP TIME: = 3ns MINIMUM
SC
t
HOLD TIME: = 3ns MINIMUM
HC
≥
t t
SYNC PULSE WIDTH:
PW_SYNC_IN CLK
AD9361 BB Multichip Synchronization SYNC_IN Pulse Timing (BBPLL Internal REF_CLK Set to 1×)
t
CLK
t
OD
SYNCHRONIZES
t 1/f
=
CLK REF_CLK
t
OUTPUT DELAY: = 1ns MINIMUM
OD
t
SETUP TIME: = 3ns MINIMUM*
SC
t
HOLD TIME: = 3ns MINIMUM*
HC
≥
t t
SYNC PULSE WIDTH:
PW_SYNC_IN CLK
*RELATIVE TO RISING AND FALLING EDGE OF REF_CLK.
AD9361 BB Multichip Synchronization SYNC_IN Pulse Timing (BBPLL internal REF_CLK Set to 2×)
cannot be used if the 1/2× or 1/4× options are selected for
the internal BBPLL REF_CLK. Note that the SYNC_IN
pulse rising edge must have a delay from the REF_CLK
input to XTALN to ensure synchronization. This action
synchronizes the BBPLL of each device to the same
reference clock.
6. Once the BBPLLs are synchronized, clear the MCS BBPLL
Enable bit, and set the MCS Digital Clocks Enable bit while
keeping the MCS BB Enable bits set. This enables MCS to
synchronize the digital clock dividers.
7. After this register write, input another rising-edge pulse
simultaneously to the SYNC_IN pin of each device. This
action synchronizes the data clock of each device to the
same reference clock. The timing requirements of this
signal are identical to those for the first SYNC_IN pulse.
The results of this action can be observed by monitoring
the DATA_CLK output of each device and noting their
relative phases before and after the second SYNC_IN pulse
is received.
8. After synchronization is complete, clear the MCS Digital
CLK Enable and MCS BB Enable bits to prevent any
accidental triggering of the synchronization function.
t t t
OD SC HC
t
PW_SYNC_IN
PULSE 1
SYNCHRONIZES
BBPLLs
t t
SC HC
t
PW_SYNC_IN
PULSE 1
BBPLLs
Rev. A | Page 88 of 128
AD9361 Reference Manual
t t t
OD SC HC
t
PW_SYNC_IN
PULSE 2
SYNCHRONIZES
DIGITAL SAMPLING
CLOCKS
t t t
OD SC HC
t
PW_SYNC_IN
PULSE 2
SYNCHRONIZES
DIGITAL SAMPLING
CLOCKS