Main Pll Block - Analog Devices AD9361 Reference Manual

AD9361 Reference Manual

MAIN PLL BLOCK

The independent Rx and Tx PLLs use fractional-N techniques
to achieve the channel synthesis. The entire PLL is integrated
on-chip, including the VCO and the loop filter. The PLL always
operates over the range of 6 GHz 12 GHz. The charge pump
current is programmable as are all of the loop filter components
allowing optimization of performance parameters for almost
any application.
FOR BEST
PERFORMANCE
F = 35MHz TO 80MHz
REF
F REF =
10MHz TO 80MHz
PFD
F REF =
5MHz TO 320MHz
÷
2
4
÷
×2
0.1mA TO 6.4mA
Σ-Δ
MODULATOR
VCO INPUT
6GHz TO 12GHz
PROGRAMMABLE
INTEGRATED LOOP
FILTER
CHARGE
PUMP
UP
DN
0µA TO 787.5µA
12.5µA STEPS
B COUNTER 8/9
PRE-SCALER
A COUNTER
Figure 4. PLL Synthesizer Block Diagram (Rx and Tx Synthesizers are Identical)
÷ 2 ÷ 2 ÷
I I
Q Q
Rev. A
Configuration for a given frequency consists of a combination
of calculating the required divider values and referring to an
Analog Devices supplied lookup table to configure the VCO for
stable performance over temperature. The main PLL output is
divided by the VCO divider block to create the frequency bands
that allow the device to operate continuously from 70 MHz to
6 GHz. Figure 5 shows how the bands are created. The
synthesizer configuration registers, loop filter, integer and
fractional words, and VCO divider are calculated in the
ad9361_rx_lo_freq and ad9361_tx_lo_freq function calls.
100µF VCO LDO OUT
VCO
LDO
VDDA1P1 -VCO
LC VCO
6GHz TO 12GHz
FO CAL
ALC CAL
2 ÷2 ÷2 ÷2
I
I Q
Q
MUX /SELECTABLE BUFFERS
LO LO
I Q
47MHz TO 6GHz
Figure 5. VCO Divider
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VCO LDO IN
CONNECTED EXTERNALLY
NECESSARY FOR LDO STABILITY
1Ω
1µF
CERAMIC
TO
VCO DIVIDER
BLOCK
÷2
UG-570