Dual Port Fdd Functional Timing (Cmos) - Analog Devices AD9361 Reference Manual

UG-570

DUAL PORT FDD FUNCTIONAL TIMING (CMOS)

The timing diagrams in Figure 74 and Figure 75 illustrate the relationship among the bus signals in dual port full duplex mode. Note that
because 2R1T and 1R2T systems follow the 2R2T timing diagrams, they are omitted from Figure 74 and Figure 75.
1R1T, DDR, FDD, DUAL PORT, 0X010 = 0XC8, 0X011 = 0X00, 0X012 = 0X02
DATA _ CLK
RX _ FRAME
R1_I[11:0]
P 0 _ D [11 :0 ]
2R2T, DDR, FDD, DUAL PORT, 0X010 = 0XC8, 0X011 = 0X00, 0X012 = 0X02
DATA _ CLK
RX _ FRAME
R1_I[11:0] R1_Q[11:0]
P 0 _ D [11 :0 ]
1R1T, DDR, FDD, DUAL PORT, 0X010 = 0XC8, 0X011 = 0X00, 0X012 = 0X02
FB _ CLK
TX_ FRAME
0 T1_I[11:0]
P0 _ D [11 :0 ]
2R2T, DDR, FDD, DUAL PORT, 0X010 = 0XC8, 0X011 = 0X00, 0X012 = 0X02
FB _ CLK
TX_ FRAME
0 T1_I[11:0] T1_Q[11:0]
P0 _ D [11 :0 ]
R1_Q[11:0] R1_I[11:0]
R1_I[11:0] R1_Q[11:0] R1_I[11:0]
Figure 74. Receiver Data Path, Dual Port FDD (Full Port)
T1_Q[11:0] T1_I[11:0]
T1_I[11:0] T1_Q[11:0] T1_I[11:0]
Figure 75. Transmit Data Path, Dual Port FDD (Full Port)
Rev. A | Page 104 of 128
AD9361 Reference Manual
R1_Q[11:0]
R1_Q[11:0] R1_I[11:0] R1_Q[11:0]
T1_Q[11:0]
T1_Q[11:0] T1_I[11:0] T1_Q[11:0]
R1_I[11:0] R1_Q[11:0]
R1_I[11:0] R1_Q[11:0] R1_I[11:0]
T1_I[11:0] T1_Q[11:0]
T1_I[11:0] T1_Q[11:0] T1_I[11:0]
R1_Q[11:0]
T1_Q[11:0]