Analog Devices AD9361 Reference Manual page 28

UG-570
FB_CLK
ENABLE
TXNRX
ENSM STATE[3:0] WAIT
FB_CLK
SPIWRITE
ENABLE
TXNRX
ENSM STATE[3:0] WAIT
FDD Independent Control
When the AD9361 is in FDD mode, the FDD independent
control option allows the receive chain and transmit chain to be
enabled independently. This mode is enabled by setting the
FDD External Control Enable bit (0x015[D7]). Note that SPI
writes must be used to move the ENSM into the FDD state.
Then the ENABLE and TXNRX pins are internally remapped to
Force Rx On and Force Tx On, respectively. Once in the FDD
state, the control combinations in Table 14 are allowed.
Table 14. ENABLE/TXNRX Pin Alternative Functionality
Pin Level Description
ENABLE low, Rx and Tx signal chains disabled (Operates
TXNRX low like ALERT state)
ENABLE high, Rx signal chain enabled, Tx signal chain
TXNRX low disabled (Operates like Rx state)
ENABLE low, Rx signal chain disabled, Tx signal chain
TXNRX high enabled (Operates like Tx state)
ENABLE high, Rx signal chain enabled, Tx signal chain
TXNRX high enabled. (Operates like FDD state)
POWER UP VCO
ALERT
LDO
Figure 12. ENABLE Pulse Mode, FDD (Minimum Pulse Width = One FB_CLK Cycle)
POWER UP VCO
ALERT
LDO
Figure 13. ENABLE Level Mode, FDD
FDD ALERT
FDD ALERT
Note that since the ENSM always stays in the FDD state, it
never moves to the FDD FLUSH state. Therefore, the BBP must
allow enough time after enabling the receive chain for the
digital filters to flush, and enough time after sending Tx data
for the Tx to finish its transmission before disabling the
corresponding signal chain. If Tx_FRAME is held low, the data
port in the AD9361
Note that in pulse mode the BBP should send pulses on the
ENABLE pin to enable/disable the Rx signal chain. Pulses sent
on the TXNRX pin will enable/disable the Tx signal chain.
When using a SPI write to move from ALERT into the FDD
state, both the Rx and Tx signal chains start disabled until the
first pulse is received. The pulse should have a minimum pulse
width of one FB_CLK cycle. No maximum pulse width is
defined; the pulse is edge detected and internally generates a
one cycle wide pulse.
Rev. A
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AD9361 Reference Manual
FDD ALERT
FDD ALERT
will force zeros into the Tx data path.