Sleep State - Analog Devices AD9361 Reference Manual

UG-570

SLEEP STATE

The AD9361 initially powers up in a very low power state called
the SLEEP state. In this state, the
powered up; however, all internal clocks and other circuits are
powered down. After power up, the BBP programs the
using the SPI port and runs the internal calibrations necessary
for optimal performance. After normal transmit/receive
operation, if the AD9361 is not required for radio activity, the
BBP can instruct the AD9361
minimize power consumption.
The SLEEP state is technically the ENSM WAIT state with the
digital clocks turned off. When returning to the SLEEP state, all
calibration results will be stored because the
registers remain powered up.
Sleep Procedure (Assumes Current State = ALERT)
1. Disable VCO calibrations to prevent VCO settings from
being overwritten by possible automatic calibrations.
SPIWrite 0x230 = 0x55
calibration, set 0x230[0]
SPIWrite 0x270 = 0x55
calibration, set 0x270[0]
2. Move ENSM from ALERT to the WAIT state using the SPI
port. Note that when using FDD, only the Force Tx On bit
controls the ENSM. If using TDD, using Force Rx On will
limit energy being transmitted from the AD9361. In either
case, it is recommended to power down the external PA
before moving the AD9361
SPIWrite 0x014 = 0x00
0x014[0]
SPIWrite 0x014 = 0x20
setting Force Tx On bit in 0x014[5])
WAIT
(six ADC_CLK/64 clock cycles)
SPIWrite 0x014=0x00
clearing 0x014[5])
SPIWrite 0x009=0x00
state)
AD9361 SPI registers are
AD9361
to return to the SLEEP state to
AD9361 SPI
Disable Rx VCO
Disable Tx VCO
into the FDD or Tx states.
Clear the To Alert bit in
Move to FDD state (by
Wait for FDD flush time
Move to Wait State (by
Turn off all clocks (sleep
3. The AD9361
4. To wake up the AD9361, enable digital clocks and BBPLL,
and then move into the ALERT state.
SPIWrite
(assumes external clock in this case)
WAIT
(BBPLL lock bit in 0x5E[7], locked =1)
SPIWrite
force Alert state
SPIWrite
calibration, clear 0x230[0]
SPIWrite
calibration, clear 0x270[0]
Calibrations After Waking from SLEEP
Although the previous calibration results are stored through the
SLEEP state, some calibrations may need to be updated if time
permits. For instance, the
DC offset over time once in the active receive state. The first
time back into the Rx or FDD states, the DC offset may not be
optimal. Running the RF DC Offset Calibration may improve
the DC offset for the first time back in the Rx state. Another
advantage is the calibration stores RF DC offset corrections for
all front-end gain indexes. The tracking mode only allows the
RF DC offset to update at the current gain index.
If using TDD, the Rx VCO and/or Tx VCO used first will need
to be calibrated before moving into the Rx or Tx state. This can
be accomplished by toggling the TXNRX after enabling VCO
calibrations in Register 0x230 and Register 0x270. The TxRNX
edge triggers the calibration to occur. In FDD, a VCO calibra-
tion should not be required.
Rev. A | Page 30 of 128
AD9361 Reference Manual
is now in the SLEEP state.
0x009 = 0x17 Turn on all clocks
Wait for BBPLL to lock
0x014 = 0x05 Set the To Alert bit and
0x230 = 0x54 Allow Rx VCO
0x270 = 0x54 Allow Tx VCO
AD9361 normally is set to track out