Data Bus Idle And Turnaround Periods (Cmos); Data Path Timing Parameters (Cmos) - Analog Devices AD9361 Reference Manual

AD9361 Reference Manual
DATA BUS IDLE AND TURNAROUND PERIODS
(CMOS)
The P0_D[11:0] and P1_D[11:0] bus signals are usually actively
driven by the BBP or by the AD9361. During any idle periods,
the data bus values are ignored by both components. Both
ports, however, must have valid logic levels even if they are
unused.
Table 49. Data Path Timing Constraint Values
Parameter Min
t 16.276 ns
CP
t 45% of t
MP CP
t 1 ns
SC
t 0 ns
HC
t 1 ns
STx
t 0 ns
HTx
t 0 ns
DDRx
t 0 ns
DDDV
t t
ENPW CP
t t
TXNRXPW CP
t 0 ns
TXNRXSU
t 2 × t
RPRE CP
t 2 × t
RPST CP
Figure 76. Data Port Timing Parameter Diagrams – Data Reference Clocks and Hardware Control Inputs (CMOS Bus Configuration)
t t
DDRX, DDDV
DATA_CLK_P
FB_CLK_P
ENABLE
TXNRX
TX_FRAME
RX_FRAME
P0_D[11:0] RI RQ RI
Figure 77. Data Port Timing Parameter Diagrams – CMOS Bus Configuration (Example shown is Single Port, DDR, TDD Operation)
Typical Max Description
DATA_CLK cycle time (clock period)
55% of t DATA_CLK and FB_CLK high and/or low minimum pulse width
CP
(including effects of duty cycle distortion, period jitter, cycle-cycle jitter and half-
period jitter)
Control signal setup time to FB_CLK at
Control signal hold time from FB_CLK at
Tx data setup time to FB_CLK at
Tx data hold time from FB_CLK at
1.5 ns Rx data delay from DATA_CLK to D[11:0] outputs – 1.8 V supply
1.2 ns Rx data delay from DATA_CLK to D[11:0] outputs – 2.5 V supply
1.0 ns Rx data delay from DATA_CLK to Rx_FRAME
ENABLE pulse width (edge-detected by FB_CLK)
TXNRX pulse width (edge-detected by FB_CLK)
TXNRX setup time to ENABLE
Time at which BBP stops driving D[11:0] before a receive burst, TDD
Time at which BBP starts driving D[11:0] after a receive burst, TDD
DATA_CLK_P
FB_CLK_P
1
ENABLE
1
THE SAME TIMING RULES APPLY TO TXNRX.
t t
DDRX, DDDV
t
ENPW
t
RPST
RQ RI RQ RI RQ

DATA PATH TIMING PARAMETERS (CMOS)

The timing parameters in Table 49 are listed to provide
guidance when interfacing the
shows the relationship between the data clocks and the
hardware control inputs. Figure 77 show the relationship
among all other parameters.
AD9361
AD9361
t t
CP MP
t
SC
t
HC
t
t
STX
STX
t
HTX
t
TXNRXSU
t
TXNRXPW
TI TQ TI TQ TI TQ TI TQ
Rev. A
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AD9361 to a BBP. Figure 76
AD9361 inputs (ENABLE, TXNRX)
AD9361 inputs (ENABLE, TXNRX)
inputs
inputs
t
HTX
t
TXNRXSU
t
RPRE
UG-570
RI RQ RI RQ