Bbpll Vco Calibration; Rf Synthesizer Charge Pump Calibration; Rf Synthesizer Vco Calibration - Analog Devices AD9361 Reference Manual

UG-570

BBPLL VCO CALIBRATION

The BBPLL VCO calibration must be run during initialization
of the AD9361 device. This calibration is run as part of the
ad9361_bbpll_set_rate function. The maximum calibration
time is calculated in Equation 1.

=

BBPLL
max VCOcalTime
REF


RF SYNTHESIZER CHARGE PUMP CALIBRATION

The charge pump calibration must be run once during
initialization of the AD9361
the up and down currents for the RF PLL's charge pump, and is
run during the ad9361_txrx_synth_cp_calib function. This
calibration must be run the first time the
the ALERT state. The calibration completes after a maximum of
36864 (Scaled_REF_CLK_IN) cycles.

RF SYNTHESIZER VCO CALIBRATION

The AD9361 contains two synthesizers. When using TDD
mode, the Rx synthesizer is only enabled when TXNRX is low.
The Tx synthesizer is only enabled when TXNRX is high.
During initial calibrations, it is recommended to set the
AD9361 device into FDD mode to enable both synthesizers
while in the ALERT state to simplify calibrations.
=
RFPLL
max VCOcalTime , us
8
�������� = +
where:
( ������
������
2
40
������ ������
�������� = �
������_������ × ����������
������
�� = 2
( 7+VCO Cal Count )
����������
Table 3. Example Calculated VCO Calibration Times for FDD Default Settings
VCO Cal Count REF_CLK
3 19.20
3 30.72
3 40.00
Table 4. Example Calculated VCO Calibration Times for TDD Defaults
VCO Cal Count REF_CLK
1 19.20
1 30.72
1 40.00
DivideSett ing 
× 
3456
×
_ CLK Scale

device. This calibration matches
AD9361 device enters
+
 12 N
+ + count
wait 
2
us 2
REF _ CLK

18
× ���������� )
�
Scale wait
2 0.885
2 0.553
2 0.425
Scale wait
2 0.885
2 0.553
2 0.425
The VCO calibration is run during the ad9361_set_rx_lo_freq
and ad9361_set_tx_lo_freq functions. First, set up any
synthesizer setup registers, then write the fractional frequency
words, followed by the integer frequency word last. The
calibration time can be traded off with calibration accuracy. It is
recommended for FDD applications, to use the longest
calibration for better accuracy since once in the FDD state, it
may be a long time before a synthesizer VCO calibration occurs
(1)
again. In TDD, the calibration time will need to be set to meet
the TDD turnaround time, while achieving the most accurate
calibration possible. In TDD, the Rx VCO calibration will occur
each time the receiver synthesizer is powered up (when TxRNX
switches from high to low logic level). The Tx VCO calibration
will occur each time the transmitter synthesizer is powered up
(when TXNRX switches from low to high logic level). See
Equation 2 for the calibration time.
The VCO calibrations can be masked (disabled) for certain
cases such as the fast lock synthesizer mode, or when an HFDD
application is required. Using the FDD Synth LUT instead of
the TDD Synth LUT could be used to acquire a temperature
stable lock for cases where there is not time to run the VCO
calibration in TDD.
Calibration completion can be detected by reading the Rx PLL
Lock bit and the Tx PLL Lock bit. The lock bits will read Logic 1
when the PLLs are locked. The bits are also available on the
control output pins.

+ ×
wait 
9
ALC
×
Scale

(µs) wait (µs)
2 ALC
1.042
0.651
0.500
(µs) wait (µs)
2 ALC
1.042
0.651
0.500
Rev. A | Page 8 of 128
AD9361 Reference Manual
N Calibration Time (µs)
count
1024 255.073
1024 160.171
1024 123.475
N Calibration Time (µs)
count
256 75.073
256 47.671
256 37.075
(2)