Rf Dc Cal Bit; Maximum Full Table/Lmt Table Index; External Lna - Analog Devices AD9361 Reference Manual

AD9361 Reference Manual

RF DC CAL BIT

As referenced in the RF DC Offset Calibration section, the RF DC
Cal bit is set for unique combinations of LMT gains. Setting this
bit forces the RF DC calibration algorithm to reduce RF DC offset
at those gain indices that involve unique LMT gain settings. In a
split gain table, each index will have this bit set as each index is
likely a unique LMT gain configuration. In a full table, each index
will not have a unique LMT gain setting. There may be several
gain indices using the same LMT configuration while the LPF
gain changes for each index. In this case, set the RF DC Cal bit in
the lowest index of the unique LMT gain. In Table 32, note that
the RF DC Cal bit is set for Index 0 but not set for Indices 1
through 7. In all of these indices, only LPF gain is changing so the
RF DC Cal bit is only set for one index. The RF DC offset
correction words used for index 0 is also used for the higher
indices.

MAXIMUM FULL TABLE/LMT TABLE INDEX

All Analog Devices suggested gain tables have a maximum full
table index of 76(d). The split table maximum index is 40(d). The
Maximum Full Table/LMT Table Index register sets the highest
gain table index that is calibrated as described in the RF DC Cal
Bit section. The chip default is 76(h) so if a suggested full table is
used, no change is required. If the BBP programs a gain table with
a different maximum index or a split table is used, this value must
be changed to the proper maximum index value.

EXTERNAL LNA

An external LNA may be added to the receive path to improve the
system noise figure. All gain control modes work seamlessly with
external LNAs, whether they are fixed gain devices or devices that
can be bypassed with the use of a control signal. Note that the
maximum single-ended level allowed at an
+2.5 dBm peak. The system engineer should perform an analysis
of the maximum possible signal at the external LNA input added
to the external LNA gain to determine if the external LNA gain is
acceptable. If the signal level at the
greater than the maximum allowable level, then an external LNA
with lower gain or an attenuator must be used.
Fixed-gain LNAs are external amplifiers (or attenuators) that
always provide a nominal amount of gain. This gain is not
controllable and the LNA cannot be bypassed. In this case, there
are no programming changes necessary for the AD9361.
AD9361 RF pin is
AD9361 RF input will be
Rev. A
Variable-gain external LNAs use a control signal to select between
two different gains. Usually one is the high gain setting and the
other is the low gain or bypass setting, which is typically a loss.
The external LNA would use high gain in most conditions unless
the input to the internal LNA is too high (+2.5 dBm peak). For
those conditions, the external LNA would use low gain (bypass
mode).
If manual gain mode is used, then there are two methods of
controlling the external LNA gain. In the first method, the BBP
controls the gain using a GPO pin connected to the external LNA.
Since the BBP controls the gain in the AD9361, it also can control
the gain of the external LNA. In the second method, the gain
table in conjunction with an
LNA. A bit in the gain table drives GPO0 for Rx1 and GPO1 for
Rx2. Setting this bit to a zero results in a low GPO output level
while a one results in a high GPO output level. To route the
external LNA bits set in the gain table to GPO pins, set the
External LNA1 control and External LNA2 control bits.
For AGC modes, the AD9361
since the changes will occur quickly and the BBP will not have
knowledge of the gain index that is used until it is selected by the
AGC.
Every time the gain changes, the gain control algorithm waits for
a duration equal to the Peak Wait Time while the analog signal
path settles. This value should be increased to allow for the
settling time of the external LNA, otherwise, the peak detectors
will be enabled before the analog stages have settled.
If the AD9361 will be used to measure RSSI, then the Ext LNA
High Gain and Ext LNA Low Gain registers should be
programmed with the external LNA gain values. The part
considers both values to represent positive gain in the front end
prior to the AD9361. Both registers use 0.5 dB/LSB resolution
and range from 0 dB to 31.5 dB. If the low gain value is negative
then the Ext LNA High Gain should be offset by this amount and
the Ext LNA Low Gain should be set to 0 (for example, high gain
value = 15 dB, low gain value = −5 dB, program Ext LNA High
Gain = 20 dB and Ext LNA Low Gain = 0 dB). This will prevent a
step in the RSSI value when the external LNA goes from an on to
an off condition.
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UG-570
AD9361 GPO controls the external
must control the external LNA gain