Analog Devices AD9361 Reference Manual page 115

AD9361 Reference Manual
SPI_ENB
SPI_CLK
SPI_DI
SPI_DO
WRITE TO REGISTER 0x15A, VALUE = 0x55
SPI_ENB
SPI_CLK
SPI_DI
SPI_DO
READ REGISTER 0x15A, VALUE = 0x55
Table 53 lists the timing specifications for the SPI bus. The relationship between these parameters is shown in Figure 84. This diagram
shows a 3-wire SPI bus timing diagram with these parameters marked. Note that this is a single read operation, so the bus-ready
parameter after the data is driven from the
Table 53. SPI Bus Timing Constraint Values
Parameter Min Typ
t 20 ns
CP
t 9 ns
MP
t 1 ns
SC
t 0 ns
HC
t 2 ns
S
t 1 ns
H
t 3 ns
CO
t t
HZM H
t 0 ns
HZS
t
SC
SPI_ENB
t
SPI_CLK
SPI_DI
Figure 82. Nominal Timing Diagram, SPI Write
Figure 83. Nominal Timing Diagram, SPI Read
AD9361 is not shown in the diagram.
Max Description
SPI_CLK cycle time (clock period)
SPI_CLK pulse width
SPI_ENB setup time to first SPI_CLK rising edge
Last SPI_CLK falling edge to SPI_ENB hold
SPI_DI data input setup time to SPI_CLK
SPI_DI data input hold time to SPI_CLK
8 ns SPI_CLK rising edge to output data delay (3-wire or 4-wire mode)
t Bus turnaround time after BBP drives the last address bit
CO (max)
t Bus turnaround time after
CO (max)
t
MP CP
t
S
t
H
Figure 84. 3-Wire SPI Timing with Parameter Labels, SPI Read
AD9361
Rev. A
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drives the last data bit
t
CO
t
HZM
UG-570
t
HC