Data Path Timing Parameters (Lvds) - Analog Devices AD9361 Reference Manual

AD9361 Reference Manual
The following bits are not supported in LVDS mode:
•
Swap Ports—In LVDS mode, P0 is Tx and P1 is Rx. This configuration cannot be changed.
•
Single Port Mode —Both ports are enabled in LVDS mode.
•
FDD Full Port—Not supported in LVDS.
•
FDD Alt Word Order—Not supported in LVDS.
•
FDD Swap Bits—Not supported in LVDS.

DATA PATH TIMING PARAMETERS (LVDS)

Table 51 lists the timing constraints for the LVDS data buses.
Table 51. Data Path Timing Constraint Values—LVDS Mode
Parameter Min Typ
t 4.069 ns
CP
t 45% of t
MP CP
t 1 ns
STx
t 0 ns
HTx
t 0.25 ns
DDRx
t 0.25 ns
DDDV
Max Description
DATA_CLK cycle time (clock period)
55% of t DATA_CLK and FB_CLK high and/or low minimum pulse width (including effects of duty
CP
cycle distortion, period jitter, cycle-cycle jitter and half-period jitter)
Tx_D[5:0], Tx_FRAME setup time to FB_CLK falling edge at
Tx_D[5:0], Tx_FRAME hold time from FB_CLK falling edge at
1.25 ns Delay from DATA_CLK to Rx_D[5:0] outputs
1.25 ns Delay from DATA_CLK to Rx_FRAME
Rev. A | Page 111 of 128
UG-570
AD9361 inputs
AD9361 inputs