Single Port Fdd Functional Timing (Cmos) - Analog Devices AD9361 Reference Manual

AD9361 Reference Manual

SINGLE PORT FDD FUNCTIONAL TIMING (CMOS)

The timing diagrams in Figure 68 and Figure 69 illustrate the relationship among the bus signals in single port FDD mode. Note that
because 2R1T and 1R2T systems follow the 2R2T timing diagrams, they are omitted from Figure 68 and Figure 69.
1R1T, DDR, FDD, SINGLE PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x04
DATA_CLK
RX_FRAME
R1_I[11:6] R1_Q[11:6]
P0_D[5:0]
P1_D[5:0]
2R2T, DDR, FDD, SINGLE PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x04
DATA_CLK
RX_FRAME
R1_I[11:6] R1_Q[11:6]
P0_D[5:0]
P1_D[5:0]
1R1T, DDR, FDD, SINGLE PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x04
FB_CLK
TX_FRAME
T1_I[11:6] T1_Q[11:6]
P0_D[11:6]
P1_D[11:6]
2R2T, DDR, FDD, SINGLE PORT, 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x04
FB_CLK
TX_FRAME
T1_I[11:6] T1_Q[11:6]
P0_D[11:6]
P1_D[11:6]
R1_I[5:0] R1_I[5:0] R1_I[11:6] R1_Q[11:6]
R1_I[5:0] R1_I[5:0] R1_I[11:6] R1_Q[11:6]
Figure 68. Receive Data Path, Single Port FDD
T1_I[5:0] T1_I[5:0] T1_I[11:6] T1_Q[11:6]
T1_I[5:0] T1_I[5:0] T1_I[11:6] T1_Q[11:6]
Figure 69. Transmit Data Path, Single Port FDD
Rev. A
R1_I[5:0] R1_I[5:0]
R1_I[5:0] R1_I[5:0]
T1_I[5:0] T1_I[5:0] T1_I[11:6] T1_Q[11:6]
0
T1_I[5:0] T1_I[5:0]
0
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R1_I[11:6] R1_Q[11:6] R1_I[5:0]
R1_I[11:6] R1_Q[11:6] R1_I[5:0]
T1_I[5:0] T1_I[5:0]
T1_I[11:6] T1_Q[11:6] T1_I[5:0]
UG-570
R1_I[5:0]
R1_I[5:0]
T1_I[5:0]