Digital Interface Specification; Overview - Analog Devices AD9361 Reference Manual

UG-570

DIGITAL INTERFACE SPECIFICATION

OVERVIEW

This section defines the parallel data ports and the serial
peripheral interface (SPI) that enable the transfer of data and
control/status information between the
Figure 63 illustrates these interfaces as well as provides a high-
level view of how the AD9361
wireless system. The data interface operates in one of two
modes: standard CMOS compatible mode or low-voltage
differential signal (LVDS) compatible mode. Each interface
possesses unique characteristics described in the following
sections.
FRONT END
AD9361 and a BBP.
and BBP are used in a broadband
2
8
12
RF
2
4
Figure 63.
When CMOS mode is used:
•
Single ended-CMOS logic compatibility is maintained.
•
Either one or both data ports may be utilized. Using two
ports allows for higher data throughput.
•
Both frequency-division duplex (FDD) and time-division
duplex (TDD) operation are supported with one data port
or two.
When LVDS mode is used:
•
Data port signaling is differential LVDS, allowing up to
12-inch PCB traces/connector interconnects between the
AD9361
•
Only the data port (including clocking and other
associated timing signals) is LVDS compatible.
•
Both FDD and TDD operation are supported.
P1_D[11:0]
P0_D[11:0]
DATA_CLK
FB_CLK
RX_FRAME
TX_FRAME
TXNRX
AUX_DAC
ENABLE
TX
EN_AGC
RX
CTRL_OUT
TX_MON
CTRL_IN
GPO
SPI_ENB
SPI_CLK
SPI_DI
SPI_DO
SYNC_IN
CLK_OUT
PLL
XTAL_N
XTAL_P
AD9361
AD9361 Interface
Rev. A | Page 90 of 128
AD9361 Reference Manual
and the BBP.
12
12
2
2
2
2
8
4
BBP