Analog Devices AD9361 Reference Manual page 39

AD9361 Reference Manual
The BBP can control manual gain in one of two ways. The default
method uses SPI writes of the gain indices. Alternatively, the BBP
can pulse the control input pins to move the gain indices.
CTRL_IN0 causes the gain index to increase for Rx1 and
CTRL_IN1 causes the gain index to decrease for Rx1. Similarly,
CTRL_IN2 causes the gain to increase for Rx2 and CTRL_IN3
causes the gain to decrease for Rx2. This mode can be configured
using the ad9361_set_rx_gain_control_mode function. The pulse
is asynchronous so setup and hold are not relevant but the time
high and low must be at least two ClkRF cycles for the
detect the event. ClkRF is the clock used at the input of the
receive FIR filters.
In full table mode, a single index for the receiver controls the
gain. If SPI writes are used to control the gain, then writing the
registers sets the gain index directly. If the control input pins are
used to control the gain, then pulsing the various pins moves the
gain index pointer(s) up and down the full table.
In split table mode, if the BBP uses SPI writes to control the gain,
then separate register writes are needed to set the LMT and LPF
gain indexes. Digital gain (if enabled) would require a third
register write. If the BBP uses the control inputs to change the
gain in split table mode, then there are two options. There are
only four control inputs but there are eight different analog gain
adjustments to make (LPF, LMT, Rx1, Rx2, increment, and
decrement for each). One option is to use an SPI bit to determine
where the gain index changes (LMT or LPF). Clearing the Use
AGC for LMT/LPF Gain bit (0x0FC[D3]) enables this option and
the Inc/Dec LMT Gain bit (0x0FC[D4]) selects the gain change
location. For this option, the gain table architecture still looks like
Figure 22. If digital gain is enabled, the BBP must change this gain
by via SPI writes. The CTRL_IN pins do not change digital gain
in split table mode.
Table 17. Manual Gain Split Table Gain Change Location vs. Index Position and Overload Location
Overload Type
Large LMT
Large LMT
Large or Small ADC
Large or Small ADC
Digital Saturation
AD9361
Gain Index Position(s)
LMT index > 0
LMT index = 0
LMT index is in upper LMT table (index > initial LMT gain limit)
LMT index is in lower LMT table (index ≤ initial LMT gain limit)
N/A
Alternatively, if the Use AGC for LMT/LPF Gain bit is set, the
AD9361 peak detectors determine where the gain changes. With
this option, the architecture of the split table changes as shown in
Figure 23. Note that the LMT table has been split into two
sections, an upper LMT table and a lower LMT table. The
dividing line is the initial LMT gain limit.
LMT MAX INDEX
(0x0FD)
to
LMT INDEX LIMIT + 1
LPF INDEX
(0x10B AND 0x10D)
LMT INDEX LIMIT
(0x11A)
LMT INDEX
(0x10A AND 0x10C)
Figure 23. Split Table in Manual Gain Mode, Control Inputs and Peak Detectors
Additionally, where overloads occur and where the gain indices
are currently pointing affects where the gain changes as noted in
Table 17. As the table demonstrates, the algorithm decreases LMT
gain first and then, when the LMT index reaches the LMT Index
Limit, the type of overload determines where the gain decreases.
Increment and decrements registers 0x0FC and 0x0FE set the
amount of gain change.
If more than one overload condition occurs simultaneously, then
LMT overloads are first priority, ADC overloads are second, and
Digital Saturation is third.
Rev. A | Page 39 of 128
LMT
UPPER
TABLE
INDEX 24
LPF
GAIN
INDEX 0
LMT
LOWER
TABLE
INDEX 0
Control Gain Indices
Change Gain in
LMT table
LPF table
LMT table
LPF table
Digital table
UG-570