Lvds Mode Data Path And Clock Signals - Analog Devices AD9361 Reference Manual

UG-570

LVDS MODE DATA PATH AND CLOCK SIGNALS

The following information describes operation of the
data path in low voltage differential signal (LVDS) mode
(ANSI-644 compatible). The
parallel data buses (P0 and P1) to transfer data samples between
the AD9361 and the BBP. The bus transfers are controlled using
simple hardware handshake signaling. In LVDS mode, both
buses are used with differential LVDS signaling.
PLL
RX
DATA
TX
DATA
CTRL
AD9361
AD9361 data path interface uses
AD9361
Figure 78.
The AD9361
ASICs and FPGAs that have LVDS capability. LVDS interfaces
are typically used when a system needs superior switching
performance in noisy environments and higher data rates than
a standard CMOS interface can provide. When utilizing LVDS
mode, it is recommended to keep all trace lengths no longer
than 12 inches and to keep differential traces close together and
at equal lengths.
DATA_CLK_P
DATA_CLK_N
RX_FRAME_P
RX_FRAME_N
RX_P[5:0]
RX_N[5:0]
TX_FRAME_P
TX_FRAME_N
TX_P[5:0]
TX_N[5:0]
FB_CLK_P
FB_CLK_N
AD9361 Data Path, LVDS Mode
Rev. A | Page 106 of 128
AD9361 Reference Manual
LVDS interface facilitates connecting to custom
BBP
FEEDBACK
CLK GEN
DATA
DATA
CTRL
RX
TX