Analog Devices AD9361 Reference Manual page 112

UG-570
DATA_CLK_P
DATA_CLK_N
RX_FRAME_P
RX_FRAME_N
RX_D[5:0]
FB_CLK_P
FB_CLK_N
TX_FRAME_P
TX_FRAME_N
TX_D[5:0]
t
CP
t
DDDV
t
DDRX
t
CP
t
STX
Figure 81. Data Port Timing Parameter Diagrams—LVDS Bus Configuration
Rev. A
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AD9361 Reference Manual
t
MP
I_M Q_M I_L Q_L I_M Q_M
t
MP
t
HTX
I_M Q_M I_L Q_L I_L Q_L
I_L Q_L
I_L Q_L