Baseband Synchronization; Overview; Multichip Synchronization - Analog Devices AD9361 Reference Manual

AD9361 Reference Manual

BASEBAND SYNCHRONIZATION

OVERVIEW

For broadband wireless access (BWA) systems, multi input-
multi output (MIMO) operation and RF beamforming are
proven techniques for maximizing throughput and efficient
spectrum utilization. Modern integrated devices with
multichannel Rx and multichannel Tx capability such as the
AD9361 make developing MIMO systems with high
performance and linearity utilizing integrated receivers,
transmitters, and synthesizers a simpler task.
Some systems may require more complex configurations that
combine multiple devices. Operating multiple devices while
trying to coordinate data for each channel of each device is not
practical for devices that operate independently without any
mechanism for aligning data timing. Data synchronization into
and out of multiple devices is required to implement such
configurations successfully.
The AD9361 is capable of providing the synchronization
necessary to implement multichannel systems. This device
contains the external control inputs and internal circuitry
needed to synchronize baseband sampling and data clocks,
allowing the system design to utilize multiple devices in parallel
with equivalent performance to a single device.

MULTICHIP SYNCHRONIZATION

The device utilizes a fractional-N synthesizer in the baseband
PLL block to generate the desired sample rate for the system.
This synthesizer generates the ADC sample clock, DAC sample
clock, and baseband digital clocks from any reference clock in
the frequency range specified for the reference clock input. For
DUPLEXER
DUPLEXER
DAC
TX1
RX1 ADC
BB
I/F
DAC
TX2
RX2 ADC
BBPLL
XTALN SYNC_IN
ADA4851-4
ADA4851-4
Figure 59. BB Multichip Synchronization Configuration
Rev. A
MIMO systems requiring more than two input or two output
channels, multiple
oscillator are required. The
accept an external reference clock and synchronize operation
with other devices using simple control logic. Each
includes its own baseband PLL that generates sampling and data
clocks from the reference clock input, so an additional control
mechanism is required to synchronize multiple devices. A
logical SYNC_IN pulse input is needed to align each device's
data clock with a common reference. Figure 59 illustrates the
connections necessary to synchronize two
oscillator output is buffered into each device using an
quad high-speed op amp as a clock buffer amplifier. Another
alternative is to use a clock buffer IC like the
distribute a buffered clock to each device while minimizing the
noise coupling between devices. The procedure following
Figure 59 explains how to synchronize two devices, but it
should be noted that additional devices could be connected in
parallel using this procedure. The total number of devices that
can be connected in parallel is limited only by the drive
capability of the clock and logic signals.
Note that this function does not include RF synchronization.
The ability to synchronize RF local oscillators is not available
with this device. Baseband PLL synchronization is the only
alignment among multiple chips that is possible using this
feature. If the MCS RF Enable bit is set then the RF LO dividers
will remain enabled in the alert state. This will allow for the RF
phase relationship between multiple devices to remain constant
throughout operation.
BB
I/F
BASEBAND
PROCESSOR
SYS BB
CLK SYNC
ADA4851-4
REFERENCE
OCILLATOR
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AD9361 devices and a common reference
AD9361 provides the capability to
AD9361
AD9548
DAC TX1
DUPLEXER
ADC RX1
DAC TX2
DUPLEXER
ADC RX2
BBPLL
SYNC_IN XTALN
UG-570
AD9361
devices. The
ADA4851-4
to