Cmos Mode Data Path And Clock Signals - Analog Devices AD9361 Reference Manual

AD9361 Reference Manual

CMOS MODE DATA PATH AND CLOCK SIGNALS

This section describes operation of the
CMOS mode. In this mode, the
use either or both parallel data ports to transfer data samples
between the AD9361 and the BBP. The bus transfers are
controlled using simple hardware handshake signaling. The two
ports can be operated in either FDD mode or bidirectional
TDD mode. In FDD mode, half of the bits transmit data and the
other half receive data simultaneously. In TDD mode, the
transmit data and receive data are alternately transferred
between the AD9361 and the BPP on the same pins during
different time slots. For applications that do not require fast
effective data rates, a single port can be used to minimize
connections to the AD9361. The data path interface consists of
the signals described in the following sections.
P0_D[11:0] and P1_D[11:0]
Both Port 0 (P0) and Port 1 (P1) have a 12-bit parallel data bus
(D[11:0]) that transfers data between the BBP and the AD9361.
Each bus is identical to the other in size and function, so
D[11:0] is used to refer to either P0 or P1. These buses can be
configured as transmit-only, receive-only, or bi-directional.
DATA_CLK
The DATA_CLK signal is provided to the BBP as a master clock
for the Rx data path. In CMOS mode, it is generated internally
and output on the DATA_CLK_P pin (DATA_CLK_N is left
unconnected). The same clock is used for P0, P1, or both ports
depending on the data bus configuration. The BBP uses this
master clock as the timing reference for the interface data
transfers and for the baseband data processing. DATA_CLK
provides source-synchronous timing with dual edge capture
(DDR) or single rising-edge capture (SDR) data transfer during
receive operation.
The DATA_CLK frequency generated depends on the system
architecture (such as, number of RF channels, degree of over-
sampling, and bandwidth mode).
AD9361 data path in
AD9361 data path interface can
Rev. A
FB_CLK
FB_CLK is a feedback (looped-back) version of DATA_CLK
driven from the BBP to the FB_CLK_P pin in CMOS mode
(FB_CLK_N is left unconnected). FB_CLK allows source
synchronous timing with rising edge capture for the burst
control signals (TX_FRAME, ENABLE, and TXNRX). FB_CLK
also provides source synchronous timing with dual edge capture
(DDR) or single rising-edge capture (SDR) for D[11:0] data
signals during Tx bursts (both P0 and P1). Note that FB_CLK
must be a feedback version of DATA_CLK (exact same
frequency and duty cycle), but there is no phase relationship
requirement between the two clock signals.
RX_FRAME
RX_FRAME is driven by the
the Rx data path (both P0 and P1). A high transition indicates
the beginning of the frame. RX_FRAME can be set to be a
single high transition at the beginning of a burst and stay high
throughout the burst, or it can be set to be a pulse train that has
a rising edge at the beginning of each frame (50% duty cycle).
In CMOS mode, this signal is output from the RX_FRAME_P
pin (RX_FRAME_N can be left unconnected).
TX_FRAME
TX_FRAME is driven by the BBP to identify valid data for the
Tx data path (both P0 and P1). A high transition indicates the
beginning of the frame. The BBP can set TX_FRAME to be a
single high transition at the beginning of a burst that stays high
throughout the burst, or it can set TX_FRAME to a pulse train
that has a rising edge at the beginning of each frame (50% duty
cycle). The AD9361
signal is input to the TX_FRAME_P pin (TX_FRAME_N is tied
to ground).
The AD9361 transmits null data (all zeros) until the first
TX_FRAME indicates valid data. This is a useful feature when
the Tx path completes a transmit operation in FDD
independent mode and the data path is not automatically
flushed. In this case, the TX_FRAME pin can be held low to
complete the data flushing operation. See the Enable State
Machine Guide section for more details.
Note that the interface requires both RX_FRAME and
TX_FRAME signals to function properly.
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AD9361 to identify valid data for
accepts either format. In CMOS mode, this
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