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Analog Devices AD9874 Manual
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Analog Devices AD9874 Manual

Analog Devices AD9874 Manual

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a
GENERAL DESCRIPTION
The evaluation board for the AD9874 and its accompanying
software provide a simple means to evaluate this highly inte-
grated IC. The AD9874 is a general-purpose IF subsystem that
digitizes a low level 10 MHz–300 MHz IF input with signal
bandwidths ranging from 6.8 kHz to 270 kHz. The signal chain
within the IC consists of a low noise amplifier, a mixer, a vari-
able gain amplifier, a band-pass - analog-to-digital converter,
and a decimation filter with programmable decimation factor.
Auxiliary blocks include clock and LO synthesizers as well as a
serial peripheral interface (SPI) port.
The functional block diagram shows the major blocks of the evalua-
tion board. The evaluation board is designed to be flexible, allowing
the user to configure it for different potential applications. The
power supply distribution block provides filtered, adjustable volt-
ages to the various supply pins of the AD9874. In the IF input
J3
TB3
TB4
Windows is a registered trademark of Microsoft Corp.
LabVIEW is a trademark of National Instruments.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
J2
IFIN
MIXER OUT
JP23
JP22
AD9874
JP18
AD9874 REVC
ANALOG
DEVICES
JP1–9
CLKIN
J6
Evaluation Board for AD9874
signal path, component pads are available to implement different
IF impedance matching networks. The LO and CLK signals can
be externally applied or internally derived from a user-supplied
VCO module interface daughter board. The reference for the
on-chip LO and CLK synthesizers can be applied via the external
FREF input or an on-board crystal oscillator.
The evaluation board is designed to interface to a PC via a National
Instruments NI 6533 series digital IO card. A XILINX FPGA
formats the data between the AD9874 and digital I/O board.
Software, developed using National Instruments' LabVIEW™
and provided as Windows
the configuration of the SPI port registers and analysis of the
AD9874's output data. This software provides a convenient
graphical user interface, allowing easy access to the various
SPI port configuration registers along with real-time frequency
and time domain analysis of its output data.
J5
LO_IN
LO VCO
MODULE INTERFACE
JP15
SW2
JP24
XILINX
FPGA
SW1
LED
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
EVAL-AD9874EB
®
executable programs, is supplied for
TB2
FREF
CRYSTAL
OSC.
JP25
U12
IDT
FIFO
U13
HEADER
TB1
© Analog Devices, Inc., 2002
J1
P1
www.analog.com

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Summary of Contents for Analog Devices AD9874

  • Page 1 SPI port configuration registers along with real-time frequency ages to the various supply pins of the AD9874. In the IF input and time domain analysis of its output data. FUNCTIONAL BLOCK DIAGRAM...

  • Page 2: Dat0

    Reference Frequency Input for LO CLK Input and Synthesizer (See Figure 6b) and CLK Synthesizer The CLK signal for the AD9874 can be supplied via an external IFIN IF Input Signal RF generator or derived from a VCO. In the former case, the...

  • Page 3: Dat3

    (DOUTS 2P.V) DOUTB_BUFF DOUTB DOUTB DOUT DOUT_BUFF DOUT DOUTA RESET_ FROM SW1 ON BOARD FIFO_DATA FIFO_DATA_BUFF LINE FIFO DRIVERS Figure 1. Block Diagram of XILINX FPGA and FIFO Used to Control Interface between AD9874 and NIDAQ Card –3– REV. 0...

  • Page 4: Dat6

    NOTE: THE GNDs OF THE TWO POWER SUPPLIES CAN BE TIED TOGETHER AT THE SUPPLIES OR ON THE BOARD AT JP24 OR JP25. POWER SUPPLY Figure 2. Typical AD9874 Evaluation Board Setup with the LO and CLK Synthesizers Disabled –4– REV. 0...

  • Page 5: Dat9

    Help button is available for each SPI register, providing a ad9874_Eval_SW_090402. vi and click OK more detailed description of its function. Figure 3. Control Panel for Programming and Tuning the AD9874 Prior to Observing Output Data –5– REV. 0...
  • Page 6 Reset—Clicking this button “resets” the AD9874 to its default logo) contains several buttons that are used to invoke various values as described in Table I of the AD9874 data sheet. Note, actions as described below in descending order. Positioning the...
  • Page 7 Observe Undecimated Modulator Output Signal button of the Window type, BW, and FFT averages. BW sets the measurement control panel. The displays show the FFT of the AD9874’s bandwidth for which the following parameters are calculated: - ADC’s undecimated output data. The clock rate and FFT signal power, in-band noise power, SNR, SFDR, and NBW.
  • Page 8 CLKN DOUTA DOUTA GNDS CLKOUT CLKOUT TP22 TP21 GNDD VDDH-DIG.INTERFACE VDDH TP18 VDDD_DIGITAL_1 VDDD VDDH Figure 6a. AD9874 Interface CLKIN VREGPQ 100UH 0.01 F IOUTC CLKP JP18 CLKIN MATCH LENGTH AGND; 3, 4, 5 0.01 F ADT1-6T CLKN 1SV228 1SV228...
  • Page 9 EVAL-AD9874EB XC17S100XL 3_3V 3_3V 3_3V DATA VCC2 XILINX CCLK VCC1 XC2S100 SPARTAN II RESET INIT OE/RESET 0.1 F TQFP144 DONE 0.1 F DGND; 5 JTAGCONN 3_3V 3_3V VCCO-B0 DONE DONE GND9 VCCO-B7 DAT0 VCCO-B4 3_3V B4IO-10 GND1 DAT1 SYNCB B0IO-7 VCCO-B3 B4IO-9 DAT2...
  • Page 10 EVAL-AD9874EB DAT3 DAT11 DAT15 DAT7 DAT2 DAT6 DAT10 DAT14 DAT1 DAT9 DAT13 DAT5 TP29 DAT0 DAT8 DAT12 DAT4 RCLK VCC4 VCC3 _MRSCTR 0.1 F 0.1 F 0.1 F 0.1 F VCC2 FS_DC VCC1 TP28 TP30 TP31 GND7 _MRS 0.1 F 0.1 F 0.1 F 0.1 F...
  • Page 11 EVAL-AD9874EB EXTERNAL POWER SUPPLY INPUTS 80MA VDIRECT 10 F 10 F TP34 TP12 80MA DGND VCOVDD VREGULATED 10 F 10 F TP35 TP36 AGND TP20 FREF TPS76333DBVT VOUT 3_3V FREF_IN AGND; 3, 4, 5 10 F 10 F TP13 0.1 F 0.1 F DOUT DOUTB...
  • Page 12 NC = 1, 2, 3, 14, 13, 12 VREGCL VDDD VDDL ADP3303A JP20 0.1 F OUT1 100pF OUT2 0.1 F JP21 NC = 1, 2, 3, 14, 13, 12 DUT BYPASS FILTERS Figure 6f. AD9874 Power Supply Interface/Filtering –12– REV. 0...