Charge Pump Current; Rfpll Loop Filter; Vco Configuration; Vco Calibration - Analog Devices AD9361 Reference Manual

UG-570

CHARGE PUMP CURRENT

The charge pump current is 6-bit programmable and varies
from 0.1 mA to 6.4 mA with 0.1 mA steps. The charge pump
current needs to be calibrated during initialization, and can
then use the Analog Devices supplied LUTs during operation.

RFPLL LOOP FILTER

The RFPLL loop filter is fully integrated on-chip and is a
standard passive Type II third-order filter with five 4-bit
programmable components (see Figure 6). The loop filter
values are included in the Analog Devices provided synthesizer
LUTs and should not be modified.
PROGRAMMABLE
INTEGRATED LOOP
FILTER
FROM
CHARGE
PUMP
C1
Figure 6. Loop Filter

VCO CONFIGURATION

VCO configuration consists of writing a few static registers
from an Analog Devices provided lookup table and then enabling
an automatic calibration procedure to configure the VCO tune
voltage (Vtune) and ALC. The VCO calibration is triggered in
one of three ways: when going from wait state to alert state,
when going from the synthesizer power-down state to the alert
state (TDD), or writing the LSBs of the Rx or Tx frequency
integer word. All LUT writes for the VCO, loop filter, and other
synthesizer settings should be written into the chip before
triggering the VCO calibration. Note that charge pump calibra-
tion should be completed before a VCO calibration is started.
When in TDD mode using hardware (ENABLE/TXNRX)
control and the device state machine is in the ALERT state, the
synthesizers power up and down with the state of the TXNRX
control line. A typical example sequence for TDD operation is
Rx-ALERT-Tx-ALERT-Rx. The BB controller sets the level of
the TXNRX line in ALERT to steer the device into the correct
next state. Then state machine advances to the next state with
the following ENABLE edge. During ALERT, as the BB
controller changes the level of TXNRX from low to high, the Rx
synthesizer turns off, the Tx synthesizer will turn on, and a Tx
VCO calibration will be triggered. Similarly, during a following
cycle, as the BB controller changes the state of TXNRX from
HIGH to LOW, the Tx synthesizer turns off, the Rx synthesizer
will turn on, and a Rx VCO calibration will be triggered.
Operationally, the BB processor should transition the TXNRX
line shortly after entering the alert mode so that the synthesizer
has as much of the time as possible between frames to calibrate
and lock. Typical TDD calibration plus lock times are on the
TO VCO
TO VCO LDO
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AD9361 Reference Manual
order of 45 µs to 60 µs. For faster lock times, refer to the TDD
Mode Faster Lock Times section.

VCO CALIBRATION

The time the calibration takes to complete is programmable.
Usually a fast calibration is appropriate for TDD systems, and a
slow calibration is appropriate for FDD. For TDD, the
synthesizer will only be on for a short time, so the danger that
temperature drift would cause it to lose lock is small. For FDD,
the synthesizer could potentially be locked indefinitely, so a
longer more accurate calibration is called for to ensure that
Vtune is sufficiently centered. Example calibration times are
shown in the RF Synthesizer VCO Calibration section.
The device includes a Fast Lock mode that makes it possible to
achieve faster than normal frequency changes by storing all
synthesizer programming information, including the VCO cal
result of this section, into either device registers or the BB
processor memory space to be recalled at a later time. See the
Fast Lock Profiles section for details.

VCO VTUNE MEASUREMENT

For debug purposes, the Vtune voltage can be output to a
package pin. The Vtune voltage is MUXed with the
corresponding (Rx or Tx) EXT_LO_IN pin. This is configured
by setting the VTune Out bit, 0x23B[6] (Rx) or 0x27B[6] (Tx).
For normal operation, these bits should be cleared.

LOCK DETECTOR

A lock detector bit is provided to indicate that the correspond-
ing synthesizer has achieved lock in the configured number of
clock. The lock detector is configured by setting the mode and
count values in the Lock Detect Config registers.
The Lock Detect Count bits set the maximum time allowed for
the RFPLL to lock. If it locks within the specified time, the lock
bits go high. The time is measured in reference clock cycles per
Table 7. It is recommended to use at least 1024 reference clock
cycles.
Table 7. Lock Detect Count
Lock Detect Count (decimal)
0
1
2
3
The Lock Detect Mode bits set the lock detect mode of
operation per Table 8. It is recommended to use run lock detect
continuously mode.
Table 8. RFPLL Lock Detect Mode
Lock Detect Mode
(Decimal)
RFPLL Lock Detect Mode
0 Disable lock detect
1 Run lock detect once, when RFPLL is enabled
2 Run lock detect continuously
3 Do not use
Reference Clock Cycles
256
512
1024
2048