Honeywell Series A User Manual page 357

Test Code Target Device(s)
T125
Lower RAM Access
Test
T126 Upper RAM Access
Test
T127 RAM Unique
Address Test
T128 RAM Destructive
Pattern Test
Pre-OS Diagnostics
T150
Application Image
Validation
T255 End of POST
Diagnostics
R400 Experion PKS Series A Fieldbus Interface Module User's Guide
July 2010
8. Maintenance, Checkout, and Calibration
8.10. FIM Self-Test Diagnostic Codes
Failure Modes
detected on each byte lane of the
upper RAM segment.
FPGA, CPU, RAM
Verifies that lower RAM segment
can be accessed as 16-bit values.
Verifies that RAM can be written as
8-bit values and read as 16-bit
values and vice versa. Verifies that
aligned and misaligned halfwords
and words can be written and read.
FPGA, CPU, RAM Verifies that upper RAM segment
can be accessed as 16-bit values.
Verifies that RAM can be written as
8-bit values and read as 16-bit
values and vice versa. Verifies that
aligned and misaligned halfwords
and words can be written and
read.FIFOs exceed a specified
limit.
FPGA, CPU, RAM Verifies that each address can be
accessed uniquely. Runs with data
parity enabled and fatal.
FPGA, CPU, RAM Checks address and data lines by
writing a non-repeating pattern over
the whole memory (upper and
lower segments), then verifying it.
Runs with data parity enabled and
fatal. Multiple patterns are used for
better coverage.
Missing Checks for valid Application Image
Application Image, stored in flash memory.
Incomplete load of
Application Image,
Bad flash memory
Confirms that self test is
successful and there is a valid
Application Image stored in Flash.
Honeywell
Function
357