Honeywell Series A User Manual page 355

Test Code Target Device(s)
T110 ICP RAM
Destructive Pattern
Test
T111 ICP ASIC Register
Access Test
T112 ICP ASIC Unique
Address Echo Test
T113 ICP Bus Lock Test
R400 Experion PKS Series A Fieldbus Interface Module User's Guide
July 2010
8. Maintenance, Checkout, and Calibration
8.10. FIM Self-Test Diagnostic Codes
Failure Modes
RAM, PLD, CPU, Checks address and data lines by
buffers writing a non-repeating pattern
over the whole memory, then
verifying it. Multiple patterns are
used for better coverage.
ICP ASIC, PLD The hardware setup parameters
ASIC-RAM having been written to the ASIC
interface some time earlier, access to the
ICP ASIC registers is verified, and
the error register is verified as
zero. The ECHO_REV operation
is used to make the ASIC write its
version register to a designated
location in shared RAM. This
value is saved in RAM. The rest of
shared RAM is verified to make
sure that only the designated
location was written.
ICP ASIC, PLD Correct access to the ICP shared
ASIC-RAM RAM from the ASIC is verified
interface through the Echo test by asking
the ASIC to write each location's
address at the address. This test
is performed once for the address
and once for the complement of
the address. Coverage is not 100
percent because only the 17 LS
address bits are supported by the
ASIC.
ICP ASIC, PlD, Verify that the ICP ASIC can be
CPU locked out of its shared RAM by
the CPU. This is accomplished
with the ASIC Echo_REV test by :
a)
b)
c)
d)
Honeywell
Function
Locking the bus,
Telling the ASIC to write a
specified address,
Looking at the address to see
that it did not change,
Unlocking the bus, and
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