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AMD SP5100 Databook
10 States of Power Rails during ACPI S1 to S5 States
SP5100 supports the ACPI states S1 to S5. Table 10-1 below shows the expected state of each power
rail during these power states.
Table 10-1: State of Each Power Rail during ACPI S1 to S5 States
Schematic
Pin name
Signal
VDDQ
+3.3_SB_R
VDD
+1.2_SB_R
S5_1.2V
S5 Power
VDD33_18
VDD33_18
Analog USB
AVDDC
2.0 Power
AVDDTX_[5:0]
USB_AVDD
/AVDDRX_[5:0]
USB Phy
USB_PHY_1.2V
digital power
AVDD_SATA
SATA Power
SATA PLL
PLLVDD_SATA
Power
SATA XTAL
XTLVDD_SATA
Power
+5-V Ref
V5_VREF
Voltage
PLL Analog
AVDDCK_3.3V
Power
PLL Digital
AVDDCK_1.2V
Power
S5 I/O
S5_3.3V
Power
PCI
PCIE_PVDD
Express
PLL Power
PCI Express
PCIE_VDDR
I/O Power
SLP_S3#
SLP_S3#
SLP_S5#
SLP_S5#
PWR_GOOD
SB_PWROK
SUS_STAT#
SUS_STAT#
RSMRST#
RSMRST#
66
States of Power Rails during ACPI S1 to S5 States
ACPI STATE
S0
S1/S2
+3.3 V
+3.3 V
+1.2 V
+1.2 V
+1.2 V
+1.2 V
3.3V
3.3V
+3.3 V
+3.3 V
+3.3 V
+3.3 V
+1.2 V
+1.2 V
+1.2 V
+1.2 V
+1.2 V
+1.2 V
+3.3 V
+3.3 V
+5.0 V
+5.0 V
+3.3 V
+3.3 V
+1.2 V
+1.2 V
+3.3 V
+3.3 V
®
+1.2 V
+1.2 V
+1.2 V
+1.2 V
+3.3 V
+3.3 V
+3.3 V
+3.3 V
+3.3 V
+3.3 V
+3.3 V
0 V
+3.3 V
+3.3 V
44409 Rev. 1.70 October 10
S3
S4/S5
0 V
0 V
0 V
0 V
+1.2 V
+1.2 V
0 V
0 V
+3.3 V
+3.3 / 0 V
+3.3 V
+3.3 / 0 V
+1.2 V
+1.2 / 0 V
0 V
0 V
0 V
0 V
0 V
0 V
0 V
0 V
0 V
0 V
0 V
0 V
+3.3 V
+3.3 V
0 V
0 V
0 V
0 V
0 V
0 V
+3.3 V
0 V
0 V
0 V
0 V
0 V
+3.3 V
+3.3 V
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