Table Arithmetic And Logic Operators - AMD 3200 - Athlon 64 2.0 GHz Processor Manual

Revision Guide for AMD Family
NBPMCxXXX Y northbridge performance monitor events XXX is the hexadecimal event counter number
programmed into MSRC
signifies the unit mask programmed into MSRC
Many register references use the notation " " to identify a range of registers For example D F x
is a shorthand notation for D F x
D F x and D F x C
Arithmetic and Logical Operators
In this document formulas follow some Verilog conventions as shown in
Table Arithmetic and Logic Operators
Operator Definition
Curly brackets are used to indicate a group of bits that are concatenated together Each set of bits is separated by a comma
E g
Bitwise OR operator E g
Logical OR operator E g
Bitwise AND operator E g
Logical AND operator E g
^
Bitwise exclusive-OR operator sometimes used as "raised to the power of" as well as indicated by the context in which it is
used E g
~
Bitwise NOT operator also known as one's complement E g ~ b
Logical NOT operator E g
Logical "is equal to" operator
Logical "is not equal to" operator
Less than or equal operator
Greater than or equal operator
*
Arithmetic multiplication operator
Arithmetic division operator
Shift left first operand by the number of bits specified by the nd operand E g
Shift right first operand by the number of bits specified by the nd operand E g
h Models h- Fh Processors
EventSelect NB PERF CTL
D F x D F x
Addr Xlate represents a -bit value the two MSBs are Addr
b b
b b
b b
b b
b ^ b b E g ^
b b logical treats multibit operand as if
Conventions
UnitMask NB PERF CTL
D F x C D F x
Table
b
b logical treats multibit operand as if
b
b logical treats multibit operand as if
b
Rev October
bits Y when specified
bits
C
D F x
and the four LSBs are Xlate
and produces a -bit result
and produces a -bit result
and produces a -bit result
b b b
b b b