Fsb_Sense[1:0] Pins; Flush# Pin; Ignne# Pin; Init# Pin - AMD Sempron 10 Datasheet

Processor with 256k l2 cache
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31994A —1 August 2004

FSB_Sense[1:0] Pins

FLUSH# Pin

IGNNE# Pin

INIT# Pin

Chapter 10
AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet
signals High above 2.5 V. Do not expose these pins to a
differential voltage greater than 1.60 V, relative to the
processor core voltage.
Refer to "VCC_2.5V Generation Circuit" found in the section,
"Motherboard Required Circuits," of the AMD Athlon™
Processor Motherboard Design Guide, order# 24363 for the
required supporting circuitry.
See "Frequency Identification (FID[3:0])" on page 27 for the
DC characteristics for FID[3:0].
FSB_Sense[1:0] pins are either open circuit (logic level of 1) or
are pulled to ground (logic level of 0) on the processor package
with a 1 kΩ resistor. In conjunction with a circuit on the
motherboard, these pins may be used to automatically detect
the front-side bus (FSB) setting of this processor. Proper
detection of the FSB setting requires the implementation of a
pull-up resistor on the motherboard. Refer to the AMD Athlon™
Processor-Based Motherboard Design Guide, order# 24363 and the
technical note FSB_Sense Auto Detection Circuitry for Desktop
Processors, order# TN26673 for more information.
Table 22 is the truth table to determine the FSB of desktop
processors.

Table 22. Front-Side Bus Sense Truth Table

FSB_Sense[1]
1
1
0
0
The FSB_Sense[1:0] pins are 3.3-V tolerant.
FLUSH# must be tied to V
debug connector is implemented, FLUSH# is routed to the
debug connector.
IGNNE# is an input from the system that tells the processor to
ignore numeric errors.
INIT# is an input from the system that resets the integer
registers without affecting the floating-point registers or the
internal caches. Execution starts at 0_FFFF_FFF0h.
Pin Descriptions
FSB_Sense[0]
0
1
1
0
with a pullup resistor. If a
CC_CORE
Bus Frequency
RESERVED
133 MHz
166 MHz
200 MHz
71

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