Table 6-81. Tap Control Instructions (25-Bit Ir); Table 6-82. Tap Instruction Bits - AMD Geode LX 600@0.7W Data Book

Processors
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33234H
DR
Instruction
Length
123FFFAh
8
127FFFAh
8
1FFFEB0h
441
1FFFFDFh
1
1FFFFFDh
29
1FFFFFEh
32
1FFFFFFh
1
Bit
Name
24
TAPSCAN#
23:18
USER[5:0]
17:16
bistEnable[4:3]
15:13
clkRatio[2:0]#
12
freezeMode
11:10
setupMode[1:0]#
9:7
bistEnable[2:0]
6
testMode#
5
forceDis#
4
selectJtagOut#
3
selectJtagIn#
2:0
OP[2:0]
534

Table 6-81. TAP Control Instructions (25-Bit IR)

IR Name
Description
BYPASS_MODES
This register is read/write.
REVID
Should be 10h for initial AMD Geode™ LX processor (upper
nibble is major rev, lower nibble is minor) changes for each
metal spin
MULTISCAN
Parallel scan (muxes scan outputs onto many chip pins)
TRISTATE
Put chip into TRI-STATE and comparison mode
BISTDR
Parallel RAM BIST - internal data register (for chip test)
IDCODE
ID Code = 0D5A1003h
BYPASS
Bypass; IEEE 1149.1 spec requires all 1s to be bypass

Table 6-82. TAP Instruction Bits

Description
Also USER[6] in the design. This is a user bit added by AMD; low indicates that an inter-
nal scan chain is accessed by the TAP.
User bits used to identify an internal scan chain or, if bit 24 is high, to access a special
internal DR, as shown in Table 6-81.
Bits 4 and 3 of the BIST enable for individual BIST chain access.
Not used in the AMD Geode™ LX processor (bits should always be high); clock ratio
controls for LogicBist.
Not used in the AMD Geode LX processor (should always be high); another clock con-
trol signal.
Not used in the AMD Geode LX processor (should always be high); these are special
BIST controller bits.
BIST[2:0] of BIST enable. Works in conjunction with bits [17:16].
Active low TEST_MODE for entire chip. Puts internal logic into scan test mode.
Active low bit TRI-STATEs all output pins.
Active low bit that allows boundary scan cells to control pads.
Active low bit that allows boundary scan cells to drive data into core logic of chip.
Opcode that selects how the JTAG chains are wired together.
GeodeLink™ Control Processor
AMD Geode™ LX Processors Data Book

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