Figure 3-4: Timing For Sb Pwr_Good De-Asserted To Rsmrst# De-Asserted; Figure 3-5: Timing For Ldt_Stp# Assertion On First Power Up (G3  S5) - AMD SP5100 Data Book

AMD SP5100 Databook
Note 10: The following figure shows the timing of SB PWR_GOOD de-asserted to RSMRST#
de-asserted during a power down sequence. However, this timing only applies to S0 to G3
state transition, because G3 state is where both signals are inactivated.
RSMRST#

Figure 3-4: Timing for SB PWR_GOOD De-asserted to RSMRST# De-asserted

Note 11: On first power up, G3  S5, or after RSMRST# assertion, the LDT_STP# will be asserted
with CPU_VDDIO power. On subsequent power up, S5  S0, the timing on T9B will apply.
Figure 3-5: Timing for LDT_STP# assertion on first power up (G3  S5)
18
SB PWR_GOOD
S0 to G3
CPU_VDDIO
LDT_STP#
SB PWRGOOD
SP5100 Power on Sequence and Timing
T14
Timing is system
depended
44409 Rev. 1.70 October 10