High-Speed Counter Terminal Allocation - Omron CP1L CPU UNIT - 06-2007 Operation Manual

High-speed Counters
5-1-5

High-speed Counter Terminal Allocation

Differential Phases, Up/
Down, or Pulse + Direction
Upper Terminal Block
(Example: AC Power
Supply Modules)
166
The following diagrams show the input terminals that can be used for high-
speed counters in each CPU Unit.
Input Terminal Arrangement for CPU Units with 14 I/O Points
High-speed counter 0
(Phase B, Decrement, or
Direction input)
Upper Terminal Block
(Example: AC Power
Supply Modules)
High-speed counter 0
(Phase A, Increment, or
Count input)
High-speed counter 1
(Phase A, Increment, or
Count input)
Input Terminal Arrangement for CPU Units with 20 I/O Points
High-speed counter 0
(Phase B, Decrement, or
Direction input)
L1
Upper Terminal Block
(Example: AC Power
Supply Modules)
High-speed counter 0
(Phase A, Increment, or
Count input)
High-speed counter 1
(Phase A, Increment, or
Count input)
Input Terminal Arrangement for CPU Units with 30 I/O Points
High-speed counter 0
(Phase B, Decrement, or
Direction input)
L1 L2/ N CO M
0 0
High-speed counter 0
(Phase A, Increment, or
Count input)
High-speed counter 1
(Phase A, Increment, or
Count input)
L1 L2/N CO M 0 1 03
0 0 02
L2/N COM 01 0 3 05
00 0 2 04
High-speed counter 1
(Phase B, Decrement, or
Direction input)
High-speed counter 1
(Phase Z or Reset input)
01 0 3 0 5 0 7 09
02 04 06 08 1 0
High-speed counter 0
(Phase Z or Reset input)
Section 5-1
High-speed counter 1
(Phase B, Decrement, or
Direction input)
High-speed counter 1
(Phase Z or Reset input)
05 07 NC N C
04 0 6 NC NC
High-speed counter 0
(Phase Z or Reset input)
High-speed counter 1
(Phase B, Decrement, or
Direction input)
High-speed counter 1
(Phase Z or Reset input)
07 09 11
06 0 8 10
High-speed counter 0
(Phase Z or Reset input)
11 01 03 05
00 02 04 NC